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Commit 09691661 authored by Aaron Sierra's avatar Aaron Sierra Committed by Brian Norris
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fsl_ifc: Support all 8 IFC chip selects



Freescale's QorIQ T Series processors support 8 IFC chip selects
within a memory map backward compatible with previous P Series
processors which supported only 4 chip selects.

Signed-off-by: default avatarAaron Sierra <asierra@xes-inc.com>
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
parent abb1cd00
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+11 −2
Original line number Original line Diff line number Diff line
@@ -61,7 +61,7 @@ int fsl_ifc_find(phys_addr_t addr_base)
	if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
	if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
		return -ENODEV;
		return -ENODEV;


	for (i = 0; i < ARRAY_SIZE(fsl_ifc_ctrl_dev->regs->cspr_cs); i++) {
	for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
		u32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
		u32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
		if (cspr & CSPR_V && (cspr & CSPR_BA) ==
		if (cspr & CSPR_V && (cspr & CSPR_BA) ==
				convert_ifc_address(addr_base))
				convert_ifc_address(addr_base))
@@ -213,7 +213,7 @@ static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
static int fsl_ifc_ctrl_probe(struct platform_device *dev)
static int fsl_ifc_ctrl_probe(struct platform_device *dev)
{
{
	int ret = 0;
	int ret = 0;

	int version, banks;


	dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
	dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");


@@ -231,6 +231,15 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev)
		goto err;
		goto err;
	}
	}


	version = ioread32be(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
			FSL_IFC_VERSION_MASK;
	banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
	dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
		version >> 24, (version >> 16) & 0xf, banks);

	fsl_ifc_ctrl_dev->version = version;
	fsl_ifc_ctrl_dev->banks = banks;

	/* get the Controller level irq */
	/* get the Controller level irq */
	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
	if (fsl_ifc_ctrl_dev->irq == NO_IRQ) {
	if (fsl_ifc_ctrl_dev->irq == NO_IRQ) {
+4 −6
Original line number Original line Diff line number Diff line
@@ -31,7 +31,6 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/fsl_ifc.h>
#include <linux/fsl_ifc.h>


#define FSL_IFC_V1_1_0	0x01010000
#define ERR_BYTE		0xFF /* Value returned for read
#define ERR_BYTE		0xFF /* Value returned for read
					bytes when read failed	*/
					bytes when read failed	*/
#define IFC_TIMEOUT_MSECS	500  /* Maximum number of mSecs to wait
#define IFC_TIMEOUT_MSECS	500  /* Maximum number of mSecs to wait
@@ -877,7 +876,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
	struct nand_chip *chip = &priv->chip;
	struct nand_chip *chip = &priv->chip;
	struct nand_ecclayout *layout;
	struct nand_ecclayout *layout;
	u32 csor, ver;
	u32 csor;


	/* Fill in fsl_ifc_mtd structure */
	/* Fill in fsl_ifc_mtd structure */
	priv->mtd.priv = chip;
	priv->mtd.priv = chip;
@@ -984,8 +983,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
		chip->ecc.mode = NAND_ECC_SOFT;
		chip->ecc.mode = NAND_ECC_SOFT;
	}
	}


	ver = ioread32be(&ifc->ifc_rev);
	if (ctrl->version == FSL_IFC_VERSION_1_1_0)
	if (ver == FSL_IFC_V1_1_0)
		fsl_ifc_sram_init(priv);
		fsl_ifc_sram_init(priv);


	return 0;
	return 0;
@@ -1045,12 +1043,12 @@ static int fsl_ifc_nand_probe(struct platform_device *dev)
	}
	}


	/* find which chip select it is connected to */
	/* find which chip select it is connected to */
	for (bank = 0; bank < FSL_IFC_BANK_COUNT; bank++) {
	for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
		if (match_bank(ifc, bank, res.start))
		if (match_bank(ifc, bank, res.start))
			break;
			break;
	}
	}


	if (bank >= FSL_IFC_BANK_COUNT) {
	if (bank >= fsl_ifc_ctrl_dev->banks) {
		dev_err(&dev->dev, "%s: address did not match any chip selects\n",
		dev_err(&dev->dev, "%s: address did not match any chip selects\n",
			__func__);
			__func__);
		return -ENODEV;
		return -ENODEV;
+16 −5
Original line number Original line Diff line number Diff line
@@ -29,7 +29,16 @@
#include <linux/of_platform.h>
#include <linux/of_platform.h>
#include <linux/interrupt.h>
#include <linux/interrupt.h>


#define FSL_IFC_BANK_COUNT 4
/*
 * The actual number of banks implemented depends on the IFC version
 *    - IFC version 1.0 implements 4 banks.
 *    - IFC version 1.1 onward implements 8 banks.
 */
#define FSL_IFC_BANK_COUNT 8

#define FSL_IFC_VERSION_MASK	0x0F0F0000
#define FSL_IFC_VERSION_1_0_0	0x01000000
#define FSL_IFC_VERSION_1_1_0	0x01010000


/*
/*
 * CSPR - Chip Select Property Register
 * CSPR - Chip Select Property Register
@@ -776,23 +785,23 @@ struct fsl_ifc_regs {
		__be32 cspr;
		__be32 cspr;
		u32 res2;
		u32 res2;
	} cspr_cs[FSL_IFC_BANK_COUNT];
	} cspr_cs[FSL_IFC_BANK_COUNT];
	u32 res3[0x19];
	u32 res3[0xd];
	struct {
	struct {
		__be32 amask;
		__be32 amask;
		u32 res4[0x2];
		u32 res4[0x2];
	} amask_cs[FSL_IFC_BANK_COUNT];
	} amask_cs[FSL_IFC_BANK_COUNT];
	u32 res5[0x18];
	u32 res5[0xc];
	struct {
	struct {
		__be32 csor;
		__be32 csor;
		__be32 csor_ext;
		__be32 csor_ext;
		u32 res6;
		u32 res6;
	} csor_cs[FSL_IFC_BANK_COUNT];
	} csor_cs[FSL_IFC_BANK_COUNT];
	u32 res7[0x18];
	u32 res7[0xc];
	struct {
	struct {
		__be32 ftim[4];
		__be32 ftim[4];
		u32 res8[0x8];
		u32 res8[0x8];
	} ftim_cs[FSL_IFC_BANK_COUNT];
	} ftim_cs[FSL_IFC_BANK_COUNT];
	u32 res9[0x60];
	u32 res9[0x30];
	__be32 rb_stat;
	__be32 rb_stat;
	u32 res10[0x2];
	u32 res10[0x2];
	__be32 ifc_gcr;
	__be32 ifc_gcr;
@@ -827,6 +836,8 @@ struct fsl_ifc_ctrl {
	int				nand_irq;
	int				nand_irq;
	spinlock_t			lock;
	spinlock_t			lock;
	void				*nand;
	void				*nand;
	int				version;
	int				banks;


	u32 nand_stat;
	u32 nand_stat;
	wait_queue_head_t nand_wait;
	wait_queue_head_t nand_wait;