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Commit 095a7e38 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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irqchip: mips-gic: Remove counter access functions 



The MIPS GIC clocksource driver is no longer using the accessor
functions provided by the irqchip driver, so remove them.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17022/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 60702867

drivers/irqchip/irq-mips-gic.c

+0 −95
Original line number Diff line number Diff line
@@ -138,101 +138,6 @@ static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) 
		  GIC_SH_MAP_TO_VPE_REG_BIT(vpe));

}



#ifdef CONFIG_CLKSRC_MIPS_GIC

u64 notrace gic_read_count(void)

{

	unsigned int hi, hi2, lo;



	if (mips_cm_is64)

		return (u64)gic_read(GIC_REG(SHARED, GIC_SH_COUNTER));



	do {

		hi = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));

		lo = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));

		hi2 = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));

	} while (hi2 != hi);



	return (((u64) hi) << 32) + lo;

}



unsigned int gic_get_count_width(void)

{

	unsigned int bits, config;



	config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));

	bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>

			 GIC_SH_CONFIG_COUNTBITS_SHF);



	return bits;

}



void notrace gic_write_compare(u64 cnt)

{

	if (mips_cm_is64) {

		gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE), cnt);

	} else {

		gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),

					(int)(cnt >> 32));

		gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),

					(int)(cnt & 0xffffffff));

	}

}



void notrace gic_write_cpu_compare(u64 cnt, int cpu)

{

	unsigned long flags;



	local_irq_save(flags);



	gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), mips_cm_vp_id(cpu));



	if (mips_cm_is64) {

		gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE), cnt);

	} else {

		gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),

					(int)(cnt >> 32));

		gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),

					(int)(cnt & 0xffffffff));

	}



	local_irq_restore(flags);

}



u64 gic_read_compare(void)

{

	unsigned int hi, lo;



	if (mips_cm_is64)

		return (u64)gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE));



	hi = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));

	lo = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));



	return (((u64) hi) << 32) + lo;

}



void gic_start_count(void)

{

	u32 gicconfig;



	/* Start the counter */

	gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));

	gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF);

	gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);

}



void gic_stop_count(void)

{

	u32 gicconfig;



	/* Stop the counter */

	gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));

	gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF;

	gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);

}



#endif



unsigned gic_read_local_vp_id(void)

{

	unsigned long ident;

include/linux/irqchip/mips-gic.h

+0 −22
Original line number Diff line number Diff line
@@ -40,11 +40,6 @@ 


#define GIC_SH_CONFIG_OFS		0x0000



/* Shared Global Counter */

#define GIC_SH_COUNTER_31_00_OFS	0x0010

/* 64-bit counter register for CM3 */

#define GIC_SH_COUNTER_OFS		GIC_SH_COUNTER_31_00_OFS

#define GIC_SH_COUNTER_63_32_OFS	0x0014

#define GIC_SH_REVISIONID_OFS		0x0020



/* Convert an interrupt number to a byte offset/bit for multi-word registers */
@@ -107,10 +102,6 @@ 
#define GIC_VPE_WD_CONFIG0_OFS		0x0090

#define GIC_VPE_WD_COUNT0_OFS		0x0094

#define GIC_VPE_WD_INITIAL0_OFS		0x0098

#define GIC_VPE_COMPARE_LO_OFS		0x00a0

/* 64-bit Compare register on CM3 */

#define GIC_VPE_COMPARE_OFS		GIC_VPE_COMPARE_LO_OFS

#define GIC_VPE_COMPARE_HI_OFS		0x00a4



#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS	0x0100

#define GIC_VPE_EIC_SS(intr)		(4 * (intr))
@@ -128,12 +119,6 @@ 
#define GIC_UMV_SH_COUNTER_63_32_OFS	0x0004



/* Masks */

#define GIC_SH_CONFIG_COUNTSTOP_SHF	28

#define GIC_SH_CONFIG_COUNTSTOP_MSK	(MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)



#define GIC_SH_CONFIG_COUNTBITS_SHF	24

#define GIC_SH_CONFIG_COUNTBITS_MSK	(MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)



#define GIC_SH_CONFIG_NUMINTRS_SHF	16

#define GIC_SH_CONFIG_NUMINTRS_MSK	(MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
@@ -258,13 +243,6 @@ extern unsigned int gic_present; 
extern void gic_init(unsigned long gic_base_addr,

	unsigned long gic_addrspace_size, unsigned int cpu_vec,

	unsigned int irqbase);

extern u64 gic_read_count(void);

extern unsigned int gic_get_count_width(void);

extern u64 gic_read_compare(void);

extern void gic_write_compare(u64 cnt);

extern void gic_write_cpu_compare(u64 cnt, int cpu);

extern void gic_start_count(void);

extern void gic_stop_count(void);

extern int gic_get_c0_compare_int(void);

extern int gic_get_c0_perfcount_int(void);

extern int gic_get_c0_fdc_int(void);