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Commit 0959db6c authored by Mark Rutland's avatar Mark Rutland Committed by Marc Zyngier
Browse files

arm64/kvm: vgic: use SYS_DESC() 



Almost all of the arm64 KVM code uses the sysreg mnemonics for AArch64
register descriptions. Move the last straggler over.

To match what we do for SYS_ICH_AP*R*_EL2, the SYS_ICC_AP*R*_EL1
mnemonics are expanded in <asm/sysreg.h>.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
Acked-by: default avatarChristoffer Dall <cdall@linaro.org>
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarChristoffer Dall <cdall@linaro.org>
parent 21bc5281

arch/arm64/include/asm/sysreg.h

+8 −0
Original line number Diff line number Diff line
@@ -185,7 +185,15 @@ 
#define SYS_ICC_HPPIR0_EL1		sys_reg(3, 0, 12, 8, 2)

#define SYS_ICC_BPR0_EL1		sys_reg(3, 0, 12, 8, 3)

#define SYS_ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)

#define SYS_ICC_AP0R0_EL1		SYS_ICC_AP0Rn_EL1(0)

#define SYS_ICC_AP0R1_EL1		SYS_ICC_AP0Rn_EL1(1)

#define SYS_ICC_AP0R2_EL1		SYS_ICC_AP0Rn_EL1(2)

#define SYS_ICC_AP0R3_EL1		SYS_ICC_AP0Rn_EL1(3)

#define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)

#define SYS_ICC_AP1R0_EL1		SYS_ICC_AP1Rn_EL1(0)

#define SYS_ICC_AP1R1_EL1		SYS_ICC_AP1Rn_EL1(1)

#define SYS_ICC_AP1R2_EL1		SYS_ICC_AP1Rn_EL1(2)

#define SYS_ICC_AP1R3_EL1		SYS_ICC_AP1Rn_EL1(3)

#define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)

#define SYS_ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)

#define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)

arch/arm64/kvm/vgic-sys-reg-v3.c

+15 −30
Original line number Diff line number Diff line
@@ -268,36 +268,21 @@ static bool access_gic_sre(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
	return true;

}

static const struct sys_reg_desc gic_v3_icc_reg_descs[] = {

	/* ICC_PMR_EL1 */

	{ Op0(3), Op1(0), CRn(4), CRm(6), Op2(0), access_gic_pmr },

	/* ICC_BPR0_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(8), Op2(3), access_gic_bpr0 },

	/* ICC_AP0R0_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(8), Op2(4), access_gic_ap0r },

	/* ICC_AP0R1_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(8), Op2(5), access_gic_ap0r },

	/* ICC_AP0R2_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(8), Op2(6), access_gic_ap0r },

	/* ICC_AP0R3_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(8), Op2(7), access_gic_ap0r },

	/* ICC_AP1R0_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(9), Op2(0), access_gic_ap1r },

	/* ICC_AP1R1_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(9), Op2(1), access_gic_ap1r },

	/* ICC_AP1R2_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(9), Op2(2), access_gic_ap1r },

	/* ICC_AP1R3_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(9), Op2(3), access_gic_ap1r },

	/* ICC_BPR1_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(12), Op2(3), access_gic_bpr1 },

	/* ICC_CTLR_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(12), Op2(4), access_gic_ctlr },

	/* ICC_SRE_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(12), Op2(5), access_gic_sre },

	/* ICC_IGRPEN0_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(12), Op2(6), access_gic_grpen0 },

	/* ICC_IGRPEN1_EL1 */

	{ Op0(3), Op1(0), CRn(12), CRm(12), Op2(7), access_gic_grpen1 },

	{ SYS_DESC(SYS_ICC_PMR_EL1), access_gic_pmr },

	{ SYS_DESC(SYS_ICC_BPR0_EL1), access_gic_bpr0 },

	{ SYS_DESC(SYS_ICC_AP0R0_EL1), access_gic_ap0r },

	{ SYS_DESC(SYS_ICC_AP0R1_EL1), access_gic_ap0r },

	{ SYS_DESC(SYS_ICC_AP0R2_EL1), access_gic_ap0r },

	{ SYS_DESC(SYS_ICC_AP0R3_EL1), access_gic_ap0r },

	{ SYS_DESC(SYS_ICC_AP1R0_EL1), access_gic_ap1r },

	{ SYS_DESC(SYS_ICC_AP1R1_EL1), access_gic_ap1r },

	{ SYS_DESC(SYS_ICC_AP1R2_EL1), access_gic_ap1r },

	{ SYS_DESC(SYS_ICC_AP1R3_EL1), access_gic_ap1r },

	{ SYS_DESC(SYS_ICC_BPR1_EL1), access_gic_bpr1 },

	{ SYS_DESC(SYS_ICC_CTLR_EL1), access_gic_ctlr },

	{ SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },

	{ SYS_DESC(SYS_ICC_IGRPEN0_EL1), access_gic_grpen0 },

	{ SYS_DESC(SYS_ICC_IGRPEN1_EL1), access_gic_grpen1 },

};



int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,