Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 090cbdd0 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'linux-4.19' of git://github.com/skeggsb/linux into drm-next 



misc fixes and cleanups for next.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv55CfRonQ0bo2XiitkCiWTjKwhsP=+ZFhoa-BaJ72Ryew@mail.gmail.com
parents 539c475d d00ddd9d

arch/arm/mm/dma-mapping.c

+6 −6
Original line number Diff line number Diff line
@@ -1151,6 +1151,11 @@ int arm_dma_supported(struct device *dev, u64 mask) 
	return __dma_supported(dev, mask, false);

}



static const struct dma_map_ops *arm_get_dma_map_ops(bool coherent)

{

	return coherent ? &arm_coherent_dma_ops : &arm_dma_ops;

}



#ifdef CONFIG_ARM_DMA_USE_IOMMU



static int __dma_info_to_prot(enum dma_data_direction dir, unsigned long attrs)
@@ -2296,7 +2301,7 @@ void arm_iommu_detach_device(struct device *dev) 
	iommu_detach_device(mapping->domain, dev);

	kref_put(&mapping->kref, release_iommu_mapping);

	to_dma_iommu_mapping(dev) = NULL;

	set_dma_ops(dev, NULL);

	set_dma_ops(dev, arm_get_dma_map_ops(dev->archdata.dma_coherent));



	pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));

}
@@ -2357,11 +2362,6 @@ static void arm_teardown_iommu_dma_ops(struct device *dev) { } 


#endif	/* CONFIG_ARM_DMA_USE_IOMMU */



static const struct dma_map_ops *arm_get_dma_map_ops(bool coherent)

{

	return coherent ? &arm_coherent_dma_ops : &arm_dma_ops;

}



void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,

			const struct iommu_ops *iommu, bool coherent)

{

drivers/gpu/drm/nouveau/dispnv04/crtc.c

+1 −1
Original line number Diff line number Diff line
@@ -1017,7 +1017,7 @@ nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 
	nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);

	nv_crtc->cursor.show(nv_crtc, true);

out:

	drm_gem_object_unreference_unlocked(gem);

	drm_gem_object_put_unlocked(gem);

	return ret;

}

drivers/gpu/drm/nouveau/dispnv50/disp.c

+31 −3
Original line number Diff line number Diff line
@@ -136,12 +136,24 @@ nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 
{

	struct nouveau_cli *cli = (void *)device->object.client;

	struct nv50_disp_core_channel_dma_v0 *args = data;

	u8 type = NVIF_MEM_COHERENT;

	int ret;



	mutex_init(&dmac->lock);



	ret = nvif_mem_init_map(&cli->mmu, NVIF_MEM_COHERENT, 0x1000,

				&dmac->push);

	/* Pascal added support for 47-bit physical addresses, but some

	 * parts of EVO still only accept 40-bit PAs.

	 *

	 * To avoid issues on systems with large amounts of RAM, and on

	 * systems where an IOMMU maps pages at a high address, we need

	 * to allocate push buffers in VRAM instead.

	 *

	 * This appears to match NVIDIA's behaviour on Pascal.

	 */

	if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)

		type |= NVIF_MEM_VRAM;



	ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);

	if (ret)

		return ret;
@@ -216,6 +228,19 @@ void 
evo_kick(u32 *push, struct nv50_dmac *evoc)

{

	struct nv50_dmac *dmac = evoc;



	/* Push buffer fetches are not coherent with BAR1, we need to ensure

	 * writes have been flushed right through to VRAM before writing PUT.

	 */

	if (dmac->push.type & NVIF_MEM_VRAM) {

		struct nvif_device *device = dmac->base.device;

		nvif_wr32(&device->object, 0x070000, 0x00000001);

		nvif_msec(device, 2000,

			if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))

				break;

		);

	}



	nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);

	mutex_unlock(&dmac->lock);

}
@@ -1007,7 +1032,7 @@ nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr, 
	mstc->port = NULL;

	drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);



	drm_connector_unreference(&mstc->connector);

	drm_connector_put(&mstc->connector);

}



static void
@@ -2231,6 +2256,9 @@ nv50_display_create(struct drm_device *dev) 
		connector->funcs->destroy(connector);

	}



	/* Disable vblank irqs aggressively for power-saving, safe on nv50+ */

	dev->vblank_disable_immediate = true;



out:

	if (ret)

		nv50_display_destroy(dev);

drivers/gpu/drm/nouveau/dispnv50/wndw.c

+0 −1
Original line number Diff line number Diff line
@@ -586,7 +586,6 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, 
	wndw->id = index;

	wndw->interlock.type = interlock_type;

	wndw->interlock.data = interlock_data;

	wndw->ctxdma.parent = &wndw->wndw.base.user;



	wndw->ctxdma.parent = &wndw->wndw.base.user;

	INIT_LIST_HEAD(&wndw->ctxdma.list);

drivers/gpu/drm/nouveau/include/nvif/object.h

+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ struct nvif_mclass { 
#define nvif_mclass(o,m) ({                                                    \

	struct nvif_object *object = (o);                                      \

	struct nvif_sclass *sclass;                                            \

	const typeof(m[0]) *mclass = (m);                                      \

	typeof(m[0]) *mclass = (m);                                            \

	int ret = -ENODEV;                                                     \

	int cnt, i, j;                                                         \

                                                                               \