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Commit 08ee77b5 authored by Axel Lin's avatar Axel Lin Committed by Thierry Reding
Browse files

pwm: lpc32xx: Properly set PWM_ENABLE bit in lpc32xx_pwm_[enable|disable] 

According to the LPC32x0 User Manual [1]:

For both PWM1 and PWM2 Control Registers:
BIT 31:
This bit gates the PWM_CLK signal and enables the external output pin
to the PWM_PIN_STATE logical level.

0 = PWM disabled. (Default)
1 = PWM enabled

So in lpc32xx_pwm_enable(), we should set PWM_ENABLE bit.
In lpc32xx_pwm_disable(), we should just clear PWM_ENABLE bit rather than
write 0 to the register which will also clear PWMx_RELOADV and PWMx_DUTY bits.

[1] http://www.nxp.com/documents/user_manual/UM10326.pdf



Signed-off-by: default avatarAxel Lin <axel.lin@ingics.com>
Tested-by: default avatarRoland Stigge <stigge@antcom.de>
Signed-off-by: default avatarThierry Reding <thierry.reding@avionic-design.de>
parent f1a8870a

drivers/pwm/pwm-lpc32xx.c

+16 −2
Original line number Original line Diff line number Diff line
@@ -77,15 +77,29 @@ static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 
static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)

static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)

{

{

	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);

	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);

	u32 val;

	int ret;



	ret = clk_enable(lpc32xx->clk);

	if (ret)

		return ret;





	return clk_enable(lpc32xx->clk);

	val = readl(lpc32xx->base + (pwm->hwpwm << 2));

	val |= PWM_ENABLE;

	writel(val, lpc32xx->base + (pwm->hwpwm << 2));



	return 0;

}

}





static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)

static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)

{

{

	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);

	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);

	u32 val;



	val = readl(lpc32xx->base + (pwm->hwpwm << 2));

	val &= ~PWM_ENABLE;

	writel(val, lpc32xx->base + (pwm->hwpwm << 2));





	writel(0, lpc32xx->base + (pwm->hwpwm << 2));

	clk_disable(lpc32xx->clk);

	clk_disable(lpc32xx->clk);

}

}