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Commit 07e45c12 authored by Anton Blanchard's avatar Anton Blanchard Committed by Michael Ellerman
Browse files

powerpc: Don't disable kernel FP/VMX/VSX MSR bits on context switch 

Writing the MSR is slow, so we want to avoid it whenever possible.

A subsequent patch will add a debug option that strictly manages the
FP/VMX/VSX unavailable bits. For now just remove it, matching what
we do in other areas of the kernel (eg enable_kernel_altivec()).

A context switch microbenchmark using yield():

http://ozlabs.org/~anton/junkcode/context_switch2.c



./context_switch2 --test=yield --fp 0 0

shows an improvement of almost 3% on POWER8.

Signed-off-by: default avatarAnton Blanchard <anton@samba.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 31a40e2b

arch/powerpc/kernel/entry_64.S

+1 −14
Original line number Diff line number Diff line
@@ -453,26 +453,13 @@ _GLOBAL(_switch) 
	SAVE_8GPRS(14, r1)

	SAVE_10GPRS(22, r1)

	mflr	r20		/* Return to switch caller */

	mfmsr	r22

	li	r0, MSR_FP

#ifdef CONFIG_VSX

BEGIN_FTR_SECTION

	oris	r0,r0,MSR_VSX@h	/* Disable VSX */

END_FTR_SECTION_IFSET(CPU_FTR_VSX)

#endif /* CONFIG_VSX */

#ifdef CONFIG_ALTIVEC

BEGIN_FTR_SECTION

	oris	r0,r0,MSR_VEC@h	/* Disable altivec */

	mfspr	r24,SPRN_VRSAVE	/* save vrsave register value */

	std	r24,THREAD_VRSAVE(r3)

END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)

#endif /* CONFIG_ALTIVEC */

	and.	r0,r0,r22

	beq+	1f

	andc	r22,r22,r0

	MTMSRD(r22)

	isync

1:	std	r20,_NIP(r1)

	std	r20,_NIP(r1)

	mfcr	r23

	std	r23,_CCR(r1)

	std	r1,KSP(r3)	/* Set old stack pointer */