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Commit 07b1fdf5 authored by Suresh Warrier's avatar Suresh Warrier Committed by Paul Mackerras
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powerpc: Add simple cache inhibited MMIO accessors 



Add simple cache inhibited accessors for memory mapped I/O.
Unlike the accessors built from the DEF_MMIO_* macros, these
don't include any hardware memory barriers, callers need to
manage memory barriers on their own. These can only be called
in hypervisor real mode.

Signed-off-by: default avatarSuresh Warrier <warrier@linux.vnet.ibm.com>
[paulus@ozlabs.org - added line to comment]
Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
parent 0eeede0c

arch/powerpc/include/asm/io.h

+29 −0
Original line number Diff line number Diff line
@@ -241,6 +241,35 @@ static inline void out_be64(volatile u64 __iomem *addr, u64 val) 
#endif

#endif /* __powerpc64__ */





/*

 * Simple Cache inhibited accessors

 * Unlike the DEF_MMIO_* macros, these don't include any h/w memory

 * barriers, callers need to manage memory barriers on their own.

 * These can only be used in hypervisor real mode.

 */



static inline u32 _lwzcix(unsigned long addr)

{

	u32 ret;



	__asm__ __volatile__("lwzcix %0,0, %1"

			     : "=r" (ret) : "r" (addr) : "memory");

	return ret;

}



static inline void _stbcix(u64 addr, u8 val)

{

	__asm__ __volatile__("stbcix %0,0,%1"

		: : "r" (val), "r" (addr) : "memory");

}



static inline void _stwcix(u64 addr, u32 val)

{

	__asm__ __volatile__("stwcix %0,0,%1"

		: : "r" (val), "r" (addr) : "memory");

}



/*

 * Low level IO stream instructions are defined out of line for now

 */