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Commit 062f5b2c authored by Thierry Reding's avatar Thierry Reding
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drm/tegra: sor: Move register definitions into a table 



After commit 932f6529 ("drm/tegra: sor: Trace register accesses"),
the debugfs register dump implementation causes excessive stack usage
and can result in build warnings. To fix this, move the register
definitions into a table and iterate over the table while dumping the
registers to debugfs.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent fbfe16df

drivers/gpu/drm/tegra/sor.c

+126 −120
Original line number Diff line number Diff line
@@ -1105,12 +1105,132 @@ static int tegra_sor_show_crc(struct seq_file *s, void *data) 
	return err;

}



#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }



static const struct debugfs_reg32 tegra_sor_regs[] = {

	DEBUGFS_REG32(SOR_CTXSW),

	DEBUGFS_REG32(SOR_SUPER_STATE0),

	DEBUGFS_REG32(SOR_SUPER_STATE1),

	DEBUGFS_REG32(SOR_STATE0),

	DEBUGFS_REG32(SOR_STATE1),

	DEBUGFS_REG32(SOR_HEAD_STATE0(0)),

	DEBUGFS_REG32(SOR_HEAD_STATE0(1)),

	DEBUGFS_REG32(SOR_HEAD_STATE1(0)),

	DEBUGFS_REG32(SOR_HEAD_STATE1(1)),

	DEBUGFS_REG32(SOR_HEAD_STATE2(0)),

	DEBUGFS_REG32(SOR_HEAD_STATE2(1)),

	DEBUGFS_REG32(SOR_HEAD_STATE3(0)),

	DEBUGFS_REG32(SOR_HEAD_STATE3(1)),

	DEBUGFS_REG32(SOR_HEAD_STATE4(0)),

	DEBUGFS_REG32(SOR_HEAD_STATE4(1)),

	DEBUGFS_REG32(SOR_HEAD_STATE5(0)),

	DEBUGFS_REG32(SOR_HEAD_STATE5(1)),

	DEBUGFS_REG32(SOR_CRC_CNTRL),

	DEBUGFS_REG32(SOR_DP_DEBUG_MVID),

	DEBUGFS_REG32(SOR_CLK_CNTRL),

	DEBUGFS_REG32(SOR_CAP),

	DEBUGFS_REG32(SOR_PWR),

	DEBUGFS_REG32(SOR_TEST),

	DEBUGFS_REG32(SOR_PLL0),

	DEBUGFS_REG32(SOR_PLL1),

	DEBUGFS_REG32(SOR_PLL2),

	DEBUGFS_REG32(SOR_PLL3),

	DEBUGFS_REG32(SOR_CSTM),

	DEBUGFS_REG32(SOR_LVDS),

	DEBUGFS_REG32(SOR_CRCA),

	DEBUGFS_REG32(SOR_CRCB),

	DEBUGFS_REG32(SOR_BLANK),

	DEBUGFS_REG32(SOR_SEQ_CTL),

	DEBUGFS_REG32(SOR_LANE_SEQ_CTL),

	DEBUGFS_REG32(SOR_SEQ_INST(0)),

	DEBUGFS_REG32(SOR_SEQ_INST(1)),

	DEBUGFS_REG32(SOR_SEQ_INST(2)),

	DEBUGFS_REG32(SOR_SEQ_INST(3)),

	DEBUGFS_REG32(SOR_SEQ_INST(4)),

	DEBUGFS_REG32(SOR_SEQ_INST(5)),

	DEBUGFS_REG32(SOR_SEQ_INST(6)),

	DEBUGFS_REG32(SOR_SEQ_INST(7)),

	DEBUGFS_REG32(SOR_SEQ_INST(8)),

	DEBUGFS_REG32(SOR_SEQ_INST(9)),

	DEBUGFS_REG32(SOR_SEQ_INST(10)),

	DEBUGFS_REG32(SOR_SEQ_INST(11)),

	DEBUGFS_REG32(SOR_SEQ_INST(12)),

	DEBUGFS_REG32(SOR_SEQ_INST(13)),

	DEBUGFS_REG32(SOR_SEQ_INST(14)),

	DEBUGFS_REG32(SOR_SEQ_INST(15)),

	DEBUGFS_REG32(SOR_PWM_DIV),

	DEBUGFS_REG32(SOR_PWM_CTL),

	DEBUGFS_REG32(SOR_VCRC_A0),

	DEBUGFS_REG32(SOR_VCRC_A1),

	DEBUGFS_REG32(SOR_VCRC_B0),

	DEBUGFS_REG32(SOR_VCRC_B1),

	DEBUGFS_REG32(SOR_CCRC_A0),

	DEBUGFS_REG32(SOR_CCRC_A1),

	DEBUGFS_REG32(SOR_CCRC_B0),

	DEBUGFS_REG32(SOR_CCRC_B1),

	DEBUGFS_REG32(SOR_EDATA_A0),

	DEBUGFS_REG32(SOR_EDATA_A1),

	DEBUGFS_REG32(SOR_EDATA_B0),

	DEBUGFS_REG32(SOR_EDATA_B1),

	DEBUGFS_REG32(SOR_COUNT_A0),

	DEBUGFS_REG32(SOR_COUNT_A1),

	DEBUGFS_REG32(SOR_COUNT_B0),

	DEBUGFS_REG32(SOR_COUNT_B1),

	DEBUGFS_REG32(SOR_DEBUG_A0),

	DEBUGFS_REG32(SOR_DEBUG_A1),

	DEBUGFS_REG32(SOR_DEBUG_B0),

	DEBUGFS_REG32(SOR_DEBUG_B1),

	DEBUGFS_REG32(SOR_TRIG),

	DEBUGFS_REG32(SOR_MSCHECK),

	DEBUGFS_REG32(SOR_XBAR_CTRL),

	DEBUGFS_REG32(SOR_XBAR_POL),

	DEBUGFS_REG32(SOR_DP_LINKCTL0),

	DEBUGFS_REG32(SOR_DP_LINKCTL1),

	DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),

	DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),

	DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),

	DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),

	DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),

	DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),

	DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),

	DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),

	DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),

	DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),

	DEBUGFS_REG32(SOR_DP_CONFIG0),

	DEBUGFS_REG32(SOR_DP_CONFIG1),

	DEBUGFS_REG32(SOR_DP_MN0),

	DEBUGFS_REG32(SOR_DP_MN1),

	DEBUGFS_REG32(SOR_DP_PADCTL0),

	DEBUGFS_REG32(SOR_DP_PADCTL1),

	DEBUGFS_REG32(SOR_DP_DEBUG0),

	DEBUGFS_REG32(SOR_DP_DEBUG1),

	DEBUGFS_REG32(SOR_DP_SPARE0),

	DEBUGFS_REG32(SOR_DP_SPARE1),

	DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),

	DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),

	DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),

	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),

	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),

	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),

	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),

	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),

	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),

	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),

	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),

	DEBUGFS_REG32(SOR_DP_TPG),

	DEBUGFS_REG32(SOR_DP_TPG_CONFIG),

	DEBUGFS_REG32(SOR_DP_LQ_CSTM0),

	DEBUGFS_REG32(SOR_DP_LQ_CSTM1),

	DEBUGFS_REG32(SOR_DP_LQ_CSTM2),

};



static int tegra_sor_show_regs(struct seq_file *s, void *data)

{

	struct drm_info_node *node = s->private;

	struct tegra_sor *sor = node->info_ent->data;

	struct drm_crtc *crtc = sor->output.encoder.crtc;

	struct drm_device *drm = node->minor->dev;

	unsigned int i;

	int err = 0;



	drm_modeset_lock_all(drm);
@@ -1120,126 +1240,12 @@ static int tegra_sor_show_regs(struct seq_file *s, void *data) 
		goto unlock;

	}



#define DUMP_REG(name)						\

	seq_printf(s, "%-38s %#05x %08x\n", #name, name,	\

		   tegra_sor_readl(sor, name))



	DUMP_REG(SOR_CTXSW);

	DUMP_REG(SOR_SUPER_STATE0);

	DUMP_REG(SOR_SUPER_STATE1);

	DUMP_REG(SOR_STATE0);

	DUMP_REG(SOR_STATE1);

	DUMP_REG(SOR_HEAD_STATE0(0));

	DUMP_REG(SOR_HEAD_STATE0(1));

	DUMP_REG(SOR_HEAD_STATE1(0));

	DUMP_REG(SOR_HEAD_STATE1(1));

	DUMP_REG(SOR_HEAD_STATE2(0));

	DUMP_REG(SOR_HEAD_STATE2(1));

	DUMP_REG(SOR_HEAD_STATE3(0));

	DUMP_REG(SOR_HEAD_STATE3(1));

	DUMP_REG(SOR_HEAD_STATE4(0));

	DUMP_REG(SOR_HEAD_STATE4(1));

	DUMP_REG(SOR_HEAD_STATE5(0));

	DUMP_REG(SOR_HEAD_STATE5(1));

	DUMP_REG(SOR_CRC_CNTRL);

	DUMP_REG(SOR_DP_DEBUG_MVID);

	DUMP_REG(SOR_CLK_CNTRL);

	DUMP_REG(SOR_CAP);

	DUMP_REG(SOR_PWR);

	DUMP_REG(SOR_TEST);

	DUMP_REG(SOR_PLL0);

	DUMP_REG(SOR_PLL1);

	DUMP_REG(SOR_PLL2);

	DUMP_REG(SOR_PLL3);

	DUMP_REG(SOR_CSTM);

	DUMP_REG(SOR_LVDS);

	DUMP_REG(SOR_CRCA);

	DUMP_REG(SOR_CRCB);

	DUMP_REG(SOR_BLANK);

	DUMP_REG(SOR_SEQ_CTL);

	DUMP_REG(SOR_LANE_SEQ_CTL);

	DUMP_REG(SOR_SEQ_INST(0));

	DUMP_REG(SOR_SEQ_INST(1));

	DUMP_REG(SOR_SEQ_INST(2));

	DUMP_REG(SOR_SEQ_INST(3));

	DUMP_REG(SOR_SEQ_INST(4));

	DUMP_REG(SOR_SEQ_INST(5));

	DUMP_REG(SOR_SEQ_INST(6));

	DUMP_REG(SOR_SEQ_INST(7));

	DUMP_REG(SOR_SEQ_INST(8));

	DUMP_REG(SOR_SEQ_INST(9));

	DUMP_REG(SOR_SEQ_INST(10));

	DUMP_REG(SOR_SEQ_INST(11));

	DUMP_REG(SOR_SEQ_INST(12));

	DUMP_REG(SOR_SEQ_INST(13));

	DUMP_REG(SOR_SEQ_INST(14));

	DUMP_REG(SOR_SEQ_INST(15));

	DUMP_REG(SOR_PWM_DIV);

	DUMP_REG(SOR_PWM_CTL);

	DUMP_REG(SOR_VCRC_A0);

	DUMP_REG(SOR_VCRC_A1);

	DUMP_REG(SOR_VCRC_B0);

	DUMP_REG(SOR_VCRC_B1);

	DUMP_REG(SOR_CCRC_A0);

	DUMP_REG(SOR_CCRC_A1);

	DUMP_REG(SOR_CCRC_B0);

	DUMP_REG(SOR_CCRC_B1);

	DUMP_REG(SOR_EDATA_A0);

	DUMP_REG(SOR_EDATA_A1);

	DUMP_REG(SOR_EDATA_B0);

	DUMP_REG(SOR_EDATA_B1);

	DUMP_REG(SOR_COUNT_A0);

	DUMP_REG(SOR_COUNT_A1);

	DUMP_REG(SOR_COUNT_B0);

	DUMP_REG(SOR_COUNT_B1);

	DUMP_REG(SOR_DEBUG_A0);

	DUMP_REG(SOR_DEBUG_A1);

	DUMP_REG(SOR_DEBUG_B0);

	DUMP_REG(SOR_DEBUG_B1);

	DUMP_REG(SOR_TRIG);

	DUMP_REG(SOR_MSCHECK);

	DUMP_REG(SOR_XBAR_CTRL);

	DUMP_REG(SOR_XBAR_POL);

	DUMP_REG(SOR_DP_LINKCTL0);

	DUMP_REG(SOR_DP_LINKCTL1);

	DUMP_REG(SOR_LANE_DRIVE_CURRENT0);

	DUMP_REG(SOR_LANE_DRIVE_CURRENT1);

	DUMP_REG(SOR_LANE4_DRIVE_CURRENT0);

	DUMP_REG(SOR_LANE4_DRIVE_CURRENT1);

	DUMP_REG(SOR_LANE_PREEMPHASIS0);

	DUMP_REG(SOR_LANE_PREEMPHASIS1);

	DUMP_REG(SOR_LANE4_PREEMPHASIS0);

	DUMP_REG(SOR_LANE4_PREEMPHASIS1);

	DUMP_REG(SOR_LANE_POSTCURSOR0);

	DUMP_REG(SOR_LANE_POSTCURSOR1);

	DUMP_REG(SOR_DP_CONFIG0);

	DUMP_REG(SOR_DP_CONFIG1);

	DUMP_REG(SOR_DP_MN0);

	DUMP_REG(SOR_DP_MN1);

	DUMP_REG(SOR_DP_PADCTL0);

	DUMP_REG(SOR_DP_PADCTL1);

	DUMP_REG(SOR_DP_DEBUG0);

	DUMP_REG(SOR_DP_DEBUG1);

	DUMP_REG(SOR_DP_SPARE0);

	DUMP_REG(SOR_DP_SPARE1);

	DUMP_REG(SOR_DP_AUDIO_CTRL);

	DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS);

	DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS);

	DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER);

	DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0);

	DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1);

	DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2);

	DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3);

	DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4);

	DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5);

	DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6);

	DUMP_REG(SOR_DP_TPG);

	DUMP_REG(SOR_DP_TPG_CONFIG);

	DUMP_REG(SOR_DP_LQ_CSTM0);

	DUMP_REG(SOR_DP_LQ_CSTM1);

	DUMP_REG(SOR_DP_LQ_CSTM2);



#undef DUMP_REG

	for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {

		unsigned int offset = tegra_sor_regs[i].offset;



		seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,

			   offset, tegra_sor_readl(sor, offset));

	}



unlock:

	drm_modeset_unlock_all(drm);