Merge branch 'for-russell' of... (05d9881b) · Commits · e / devices / android_kernel_teracube_emerald

arch/arm/include/asm/sizes.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -43,6 +43,7 @@
		#define SZ_8M 0x00800000
		#define SZ_16M 0x01000000
		#define SZ_32M 0x02000000
		#define SZ_48M 0x03000000
		#define SZ_64M 0x04000000
		#define SZ_128M 0x08000000
		#define SZ_256M 0x10000000

arch/arm/mach-ixp4xx/common-pci.c

+13 −12

Original line number	Diff line number	Diff line
		@@ -411,15 +411,16 @@ void __init ixp4xx_pci_preinit(void)
		* We configure the PCI inbound memory windows to be
		* 1:1 mapped to SDRAM
		*/
		local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000);
		local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000);
		local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000);
		local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000);
		local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
		local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
		local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
		local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M);

		/*
		* Enable CSR window at 0xff000000.
		* Enable CSR window at 64 MiB to allow PCI masters
		* to continue prefetching past 64 MiB boundary.
		*/
		local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008);
		local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);

		/*
		* Enable the IO window to be way up high, at 0xfffffc00
		@@ -500,7 +501,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
		return 1;
		}

		struct pci_bus ixp4xx_scan_bus(int nr, struct pci_sys_data sys)
		struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
		{
		return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys);
		}

arch/arm/mach-ixp4xx/include/mach/cpu.h

+20 −15

Original line number	Diff line number	Diff line
		@@ -17,26 +17,31 @@
		#include <asm/cputype.h>

		/* Processor id value in CP15 Register 0 */
		#define IXP425_PROCESSOR_ID_VALUE 0x690541c0
		#define IXP435_PROCESSOR_ID_VALUE 0x69054040
		#define IXP465_PROCESSOR_ID_VALUE 0x69054200
		#define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0

		#define cpu_is_ixp42x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
		IXP425_PROCESSOR_ID_VALUE)
		#define cpu_is_ixp43x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
		IXP435_PROCESSOR_ID_VALUE)
		#define cpu_is_ixp46x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
		IXP465_PROCESSOR_ID_VALUE)
		#define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */
		#define IXP42X_PROCESSOR_ID_MASK 0xffffffc0

		#define IXP43X_PROCESSOR_ID_VALUE 0x69054040
		#define IXP43X_PROCESSOR_ID_MASK 0xfffffff0

		#define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */
		#define IXP46X_PROCESSOR_ID_MASK 0xfffffff0

		#define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \
		IXP42X_PROCESSOR_ID_VALUE)
		#define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \
		IXP43X_PROCESSOR_ID_VALUE)
		#define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \
		IXP46X_PROCESSOR_ID_VALUE)

		static inline u32 ixp4xx_read_feature_bits(void)
		{
		unsigned int val = ~*IXP4XX_EXP_CFG2;
		val &= ~IXP4XX_FEATURE_RESERVED;
		if (!cpu_is_ixp46x())
		val &= ~IXP4XX_FEATURE_IXP46X_ONLY;

		return val;
		if (cpu_is_ixp42x())
		return val & IXP42X_FEATURE_MASK;
		if (cpu_is_ixp43x())
		return val & IXP43X_FEATURE_MASK;
		return val & IXP46X_FEATURE_MASK;
		}

		static inline void ixp4xx_write_feature_bits(u32 value)

arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h

+32 −10

Original line number	Diff line number	Diff line
		@@ -604,6 +604,7 @@
		#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */

		/* "fuse" bits of IXP_EXP_CFG2 */
		/* All IXP4xx CPUs */
		#define IXP4XX_FEATURE_RCOMP (1 << 0)
		#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
		#define IXP4XX_FEATURE_HASH (1 << 2)
		@@ -619,20 +620,41 @@
		#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
		#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
		#define IXP4XX_FEATURE_PCI (1 << 14)
		#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
		#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
		#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
		#define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP \| \
		IXP4XX_FEATURE_USB_DEVICE \| \
		IXP4XX_FEATURE_HASH \| \
		IXP4XX_FEATURE_AES \| \
		IXP4XX_FEATURE_DES \| \
		IXP4XX_FEATURE_HDLC \| \
		IXP4XX_FEATURE_AAL \| \
		IXP4XX_FEATURE_HSS \| \
		IXP4XX_FEATURE_UTOPIA \| \
		IXP4XX_FEATURE_NPEB_ETH0 \| \
		IXP4XX_FEATURE_NPEC_ETH \| \
		IXP4XX_FEATURE_RESET_NPEA \| \
		IXP4XX_FEATURE_RESET_NPEB \| \
		IXP4XX_FEATURE_RESET_NPEC \| \
		IXP4XX_FEATURE_PCI \| \
		IXP4XX_FEATURE_UTOPIA_PHY_LIMIT \| \
		IXP4XX_FEATURE_XSCALE_MAX_FREQ)


		/* IXP43x/46x CPUs */
		#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
		#define IXP4XX_FEATURE_USB_HOST (1 << 18)
		#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
		#define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK \| \
		IXP4XX_FEATURE_ECC_TIMESYNC \| \
		IXP4XX_FEATURE_USB_HOST \| \
		IXP4XX_FEATURE_NPEA_ETH)

		/* IXP46x CPU (including IXP455) only */
		#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
		#define IXP4XX_FEATURE_RSA (1 << 21)
		#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
		#define IXP4XX_FEATURE_RESERVED (0xFF << 24)

		#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC \| \
		IXP4XX_FEATURE_USB_HOST \| \
		IXP4XX_FEATURE_NPEA_ETH \| \
		#define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK \| \
		IXP4XX_FEATURE_NPEB_ETH_1_TO_3 \| \
		IXP4XX_FEATURE_RSA \| \
		IXP4XX_FEATURE_XSCALE_MAX_FREQ)
		IXP4XX_FEATURE_RSA)

		#endif

arch/arm/mach-ixp4xx/ixp4xx_npe.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -575,8 +575,8 @@ int npe_load_firmware(struct npe npe, const char name, struct device *dev)
		for (i = 0; i < image->size; i++)
		image->data[i] = swab32(image->data[i]);

		if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
		print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
		if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) {
		print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on "
		"IXP42x\n");
		goto err;
		}
		@@ -596,7 +596,7 @@ int npe_load_firmware(struct npe npe, const char name, struct device *dev)
		"revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
		(image->id >> 8) & 0xFF, image->id & 0xFF);

		if (!cpu_is_ixp46x()) {
		if (cpu_is_ixp42x()) {
		if (!npe->id)
		instr_size = NPE_A_42X_INSTR_SIZE;
		else