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Commit 050d9d43 authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: cleanup job header 



Move job related defines, structure and function declarations to
amdgpu_job.h

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarJunwei Zhang <Jerry.Zhang@amd.com>
Acked-by: default avatarChunming Zhou <david1.zhou@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9a6a8075

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −45
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ 
#include "amdgpu_virt.h"

#include "amdgpu_gart.h"

#include "amdgpu_debugfs.h"

#include "amdgpu_job.h"



/*

 * Modules parameters.
@@ -600,17 +601,6 @@ struct amdgpu_ib { 


extern const struct drm_sched_backend_ops amdgpu_sched_ops;



int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,

		     struct amdgpu_job **job, struct amdgpu_vm *vm);

int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,

			     struct amdgpu_job **job);



void amdgpu_job_free_resources(struct amdgpu_job *job);

void amdgpu_job_free(struct amdgpu_job *job);

int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,

		      struct drm_sched_entity *entity, void *owner,

		      struct dma_fence **f);



/*

 * Queue manager

 */
@@ -1058,40 +1048,6 @@ struct amdgpu_cs_parser { 
	struct drm_syncobj **post_dep_syncobjs;

};



#define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0) /* bit set means command submit involves a preamble IB */

#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1) /* bit set means preamble IB is first presented in belonging context */

#define AMDGPU_HAVE_CTX_SWITCH              (1 << 2) /* bit set means context switch occured */



struct amdgpu_job {

	struct drm_sched_job    base;

	struct amdgpu_device	*adev;

	struct amdgpu_vm	*vm;

	struct amdgpu_ring	*ring;

	struct amdgpu_sync	sync;

	struct amdgpu_sync	sched_sync;

	struct amdgpu_ib	*ibs;

	struct dma_fence	*fence; /* the hw fence */

	uint32_t		preamble_status;

	uint32_t		num_ibs;

	void			*owner;

	uint64_t		fence_ctx; /* the fence_context this job uses */

	bool                    vm_needs_flush;

	uint64_t		vm_pd_addr;

	unsigned		vmid;

	unsigned		pasid;

	uint32_t		gds_base, gds_size;

	uint32_t		gws_base, gws_size;

	uint32_t		oa_base, oa_size;

	uint32_t		vram_lost_counter;



	/* user fence handling */

	uint64_t		uf_addr;

	uint64_t		uf_sequence;



};

#define to_amdgpu_job(sched_job)		\

		container_of((sched_job), struct amdgpu_job, base)



static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,

				      uint32_t ib_idx, int idx)

{

drivers/gpu/drm/amd/amdgpu/amdgpu_job.h

0 → 100644
+74 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2018 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef __AMDGPU_JOB_H__

#define __AMDGPU_JOB_H__



/* bit set means command submit involves a preamble IB */

#define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0)

/* bit set means preamble IB is first presented in belonging context */

#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1)

/* bit set means context switch occured */

#define AMDGPU_HAVE_CTX_SWITCH              (1 << 2)



#define to_amdgpu_job(sched_job)		\

		container_of((sched_job), struct amdgpu_job, base)



struct amdgpu_job {

	struct drm_sched_job    base;

	struct amdgpu_device	*adev;

	struct amdgpu_vm	*vm;

	struct amdgpu_ring	*ring;

	struct amdgpu_sync	sync;

	struct amdgpu_sync	sched_sync;

	struct amdgpu_ib	*ibs;

	struct dma_fence	*fence; /* the hw fence */

	uint32_t		preamble_status;

	uint32_t		num_ibs;

	void			*owner;

	uint64_t		fence_ctx; /* the fence_context this job uses */

	bool                    vm_needs_flush;

	uint64_t		vm_pd_addr;

	unsigned		vmid;

	unsigned		pasid;

	uint32_t		gds_base, gds_size;

	uint32_t		gws_base, gws_size;

	uint32_t		oa_base, oa_size;

	uint32_t		vram_lost_counter;



	/* user fence handling */

	uint64_t		uf_addr;

	uint64_t		uf_sequence;



};



int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,

		     struct amdgpu_job **job, struct amdgpu_vm *vm);

int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,

			     struct amdgpu_job **job);



void amdgpu_job_free_resources(struct amdgpu_job *job);

void amdgpu_job_free(struct amdgpu_job *job);

int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,

		      struct drm_sched_entity *entity, void *owner,

		      struct dma_fence **f);

#endif