Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 04cdd5af authored Jun 19, 2018 by Jerome Brunet Committed by Michael Turquette Jun 19, 2018

clk: qcom: drop CLK_SET_RATE_GATE from sdc clocks



the mmci driver (drivers/mmc/host/mmci.c) does the following sequence:
* clk_prepare_enable()
* clk_set_rate()

on SDCx_clk which is a children of SDCx_src. SDCx_src has
CLK_SET_RATE_GATE so this sequence should not be allowed but this was not
enforced. IOW, the flag is ignored. Dropping the flag won't change
anything to the current behaviour of the platform.

CLK_SET_RATE_GATE is being fixed and enforced now. If the flag was kept,
the mmci driver would receive -EBUSY when calling clk_set_rate()

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180619134051.16726-2-jbrunet@baylibre.com

parent ce397d21

drivers/clk/qcom/gcc-ipq806x.c

+0 −3

Original line number	Original line	Diff line number	Diff line
	@@ -1220,7 +1220,6 @@ static struct clk_rcg sdc1_src = {
	.parent_names = gcc_pxo_pll8,		.parent_names = gcc_pxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};
	@@ -1269,7 +1268,6 @@ static struct clk_rcg sdc3_src = {
	.parent_names = gcc_pxo_pll8,		.parent_names = gcc_pxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};
	@@ -1353,7 +1351,6 @@ static struct clk_rcg tsif_ref_src = {
	.parent_names = gcc_pxo_pll8,		.parent_names = gcc_pxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};

drivers/clk/qcom/gcc-mdm9615.c

+0 −2

Original line number	Original line	Diff line number	Diff line
	@@ -947,7 +947,6 @@ static struct clk_rcg sdc1_src = {
	.parent_names = gcc_cxo_pll8,		.parent_names = gcc_cxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};
	@@ -996,7 +995,6 @@ static struct clk_rcg sdc2_src = {
	.parent_names = gcc_cxo_pll8,		.parent_names = gcc_cxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};

drivers/clk/qcom/gcc-msm8660.c

+0 −5

Original line number	Original line	Diff line number	Diff line
	@@ -1558,7 +1558,6 @@ static struct clk_rcg sdc1_src = {
	.parent_names = gcc_pxo_pll8,		.parent_names = gcc_pxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};
	@@ -1607,7 +1606,6 @@ static struct clk_rcg sdc2_src = {
	.parent_names = gcc_pxo_pll8,		.parent_names = gcc_pxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};
	@@ -1656,7 +1654,6 @@ static struct clk_rcg sdc3_src = {
	.parent_names = gcc_pxo_pll8,		.parent_names = gcc_pxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};
	@@ -1705,7 +1702,6 @@ static struct clk_rcg sdc4_src = {
	.parent_names = gcc_pxo_pll8,		.parent_names = gcc_pxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};
	@@ -1754,7 +1750,6 @@ static struct clk_rcg sdc5_src = {
	.parent_names = gcc_pxo_pll8,		.parent_names = gcc_pxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};

drivers/clk/qcom/gcc-msm8960.c

+0 −5

Original line number	Original line	Diff line number	Diff line
	@@ -1628,7 +1628,6 @@ static struct clk_rcg sdc1_src = {
	.parent_names = gcc_pxo_pll8,		.parent_names = gcc_pxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};
	@@ -1677,7 +1676,6 @@ static struct clk_rcg sdc2_src = {
	.parent_names = gcc_pxo_pll8,		.parent_names = gcc_pxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};
	@@ -1726,7 +1724,6 @@ static struct clk_rcg sdc3_src = {
	.parent_names = gcc_pxo_pll8,		.parent_names = gcc_pxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};
	@@ -1775,7 +1772,6 @@ static struct clk_rcg sdc4_src = {
	.parent_names = gcc_pxo_pll8,		.parent_names = gcc_pxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};
	@@ -1824,7 +1820,6 @@ static struct clk_rcg sdc5_src = {
	.parent_names = gcc_pxo_pll8,		.parent_names = gcc_pxo_pll8,
	.num_parents = 2,		.num_parents = 2,
	.ops = &clk_rcg_ops,		.ops = &clk_rcg_ops,
	.flags = CLK_SET_RATE_GATE,
	},		},
	}		}
	};		};