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Commit 0357a443 authored by Sylwester Nawrocki's avatar Sylwester Nawrocki Committed by Kukjin Kim
Browse files

ARM: dts: Specify default clocks for Exynos4 camera devices 



Specify the default mux and divider clocks in device tree
to ensure the FIMC devices on Trats, Trats2, Universal_c210
and Odroid X2/U3 boards are clocked from recommended clock
source and with maximum supported frequency.
For Trats2 also the MIPI-CSIS and the camera sensor clocks
are configured, the 'clock-frequency' property is deprecated
in favour of 'assigned-clock-rates' property.

Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 432047f9

arch/arm/boot/dts/exynos4210-trats.dts

+16 −0
Original line number Original line Diff line number Diff line
@@ -431,18 +431,34 @@ 




		fimc_0: fimc@11800000 {

		fimc_0: fimc@11800000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC0>,

					<&clock CLK_SCLK_FIMC0>;

			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

			assigned-clock-rates = <0>, <160000000>;

		};

		};





		fimc_1: fimc@11810000 {

		fimc_1: fimc@11810000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC1>,

					<&clock CLK_SCLK_FIMC1>;

			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

			assigned-clock-rates = <0>, <160000000>;

		};

		};





		fimc_2: fimc@11820000 {

		fimc_2: fimc@11820000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC2>,

					<&clock CLK_SCLK_FIMC2>;

			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

			assigned-clock-rates = <0>, <160000000>;

		};

		};





		fimc_3: fimc@11830000 {

		fimc_3: fimc@11830000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC3>,

					<&clock CLK_SCLK_FIMC3>;

			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

			assigned-clock-rates = <0>, <160000000>;

		};

		};

	};

	};

};
 
};

arch/arm/boot/dts/exynos4210-universal_c210.dts

+16 −0
Original line number Original line Diff line number Diff line
@@ -473,18 +473,34 @@ 




		fimc_0: fimc@11800000 {

		fimc_0: fimc@11800000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC0>,

					<&clock CLK_SCLK_FIMC0>;

			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

			assigned-clock-rates = <0>, <160000000>;

		};

		};





		fimc_1: fimc@11810000 {

		fimc_1: fimc@11810000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC1>,

					<&clock CLK_SCLK_FIMC1>;

			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

			assigned-clock-rates = <0>, <160000000>;

		};

		};





		fimc_2: fimc@11820000 {

		fimc_2: fimc@11820000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC2>,

					<&clock CLK_SCLK_FIMC2>;

			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

			assigned-clock-rates = <0>, <160000000>;

		};

		};





		fimc_3: fimc@11830000 {

		fimc_3: fimc@11830000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC3>,

					<&clock CLK_SCLK_FIMC3>;

			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;

			assigned-clock-rates = <0>, <160000000>;

		};

		};

	};

	};

};

};

arch/arm/boot/dts/exynos4412-odroid-common.dtsi

+16 −0
Original line number Original line Diff line number Diff line
@@ -82,18 +82,34 @@ 




		fimc_0: fimc@11800000 {

		fimc_0: fimc@11800000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC0>,

					<&clock CLK_SCLK_FIMC0>;

			assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;

			assigned-clock-rates = <0>, <176000000>;

		};

		};





		fimc_1: fimc@11810000 {

		fimc_1: fimc@11810000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC1>,

					<&clock CLK_SCLK_FIMC1>;

			assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;

			assigned-clock-rates = <0>, <176000000>;

		};

		};





		fimc_2: fimc@11820000 {

		fimc_2: fimc@11820000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC2>,

					<&clock CLK_SCLK_FIMC2>;

			assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;

			assigned-clock-rates = <0>, <176000000>;

		};

		};





		fimc_3: fimc@11830000 {

		fimc_3: fimc@11830000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC3>,

					<&clock CLK_SCLK_FIMC3>;

			assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;

			assigned-clock-rates = <0>, <176000000>;

		};

		};

	};

	};

arch/arm/boot/dts/exynos4412-trats2.dts

+29 −3
Original line number Original line Diff line number Diff line
@@ -706,28 +706,51 @@ 
		pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;

		pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;

		pinctrl-names = "default";

		pinctrl-names = "default";

		status = "okay";

		status = "okay";

		assigned-clocks = <&clock CLK_MOUT_CAM0>,

				  <&clock CLK_MOUT_CAM1>;

		assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>,

					 <&clock CLK_MOUT_MPLL_USER_T>;





		fimc_0: fimc@11800000 {

		fimc_0: fimc@11800000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC0>,

					<&clock CLK_SCLK_FIMC0>;

			assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;

			assigned-clock-rates = <0>, <176000000>;

		};

		};





		fimc_1: fimc@11810000 {

		fimc_1: fimc@11810000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC1>,

					<&clock CLK_SCLK_FIMC1>;

			assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;

			assigned-clock-rates = <0>, <176000000>;

		};

		};





		fimc_2: fimc@11820000 {

		fimc_2: fimc@11820000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC2>,

					<&clock CLK_SCLK_FIMC2>;

			assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;

			assigned-clock-rates = <0>, <176000000>;

		};

		};





		fimc_3: fimc@11830000 {

		fimc_3: fimc@11830000 {

			status = "okay";

			status = "okay";

			assigned-clocks = <&clock CLK_MOUT_FIMC3>,

					<&clock CLK_SCLK_FIMC3>;

			assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;

			assigned-clock-rates = <0>, <176000000>;

		};

		};





		csis_0: csis@11880000 {

		csis_0: csis@11880000 {

			status = "okay";

			status = "okay";

			vddcore-supply = <&ldo8_reg>;

			vddcore-supply = <&ldo8_reg>;

			vddio-supply = <&ldo10_reg>;

			vddio-supply = <&ldo10_reg>;

			clock-frequency = <176000000>;

			assigned-clocks = <&clock CLK_MOUT_CSIS0>,

					<&clock CLK_SCLK_CSIS0>;

			assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;

			assigned-clock-rates = <0>, <176000000>;





			/* Camera C (3) MIPI CSI-2 (CSIS0) */

			/* Camera C (3) MIPI CSI-2 (CSIS0) */

			port@3 {

			port@3 {
@@ -741,10 +764,13 @@ 
		};

		};





		csis_1: csis@11890000 {

		csis_1: csis@11890000 {

			status = "okay";

			vddcore-supply = <&ldo8_reg>;

			vddcore-supply = <&ldo8_reg>;

			vddio-supply = <&ldo10_reg>;

			vddio-supply = <&ldo10_reg>;

			clock-frequency = <160000000>;

			assigned-clocks = <&clock CLK_MOUT_CSIS1>,

			status = "okay";

					<&clock CLK_SCLK_CSIS1>;

			assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;

			assigned-clock-rates = <0>, <176000000>;





			/* Camera D (4) MIPI CSI-2 (CSIS1) */

			/* Camera D (4) MIPI CSI-2 (CSIS1) */

			port@4 {

			port@4 {