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Commit 031994ee authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Implement WaIncreaseL3CreditsForVLVB0:vlv 



Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent c5dc5cec

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -4128,6 +4128,9 @@ 
#define COMMON_SLICE_CHICKEN2			0x7014

#define COMMON_SLICE_CHICKEN2			0x7014

# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)

# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)





#define GEN7_L3SQCREG1				0xB010

#define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000



#define GEN7_L3CNTLREG1				0xB01C

#define GEN7_L3CNTLREG1				0xB01C

#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C

#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C

#define  GEN7_L3AGDIS				(1<<19)

#define  GEN7_L3AGDIS				(1<<19)

drivers/gpu/drm/i915/intel_pm.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -4990,6 +4990,12 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(CACHE_MODE_1,

	I915_WRITE(CACHE_MODE_1,

		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));





	/*

	 * WaIncreaseL3CreditsForVLVB0:vlv

	 * This is the hardware default actually.

	 */

	I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);



	/*

	/*

	 * WaDisableVLVClockGating_VBIIssue:vlv

	 * WaDisableVLVClockGating_VBIIssue:vlv

	 * Disable clock gating on th GCFG unit to prevent a delay

	 * Disable clock gating on th GCFG unit to prevent a delay