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Commit 02e0b760 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Christoffer Dall
Browse files

arm64: kvm: Add support for 16K pages 



Now that we can handle stage-2 page tables independent
of the host page table levels, wire up the 16K page
support.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
parent 9163ee23

arch/arm64/include/asm/kvm_arm.h

+11 −2
Original line number Diff line number Diff line
@@ -114,6 +114,7 @@ 
#define VTCR_EL2_PS_MASK	TCR_EL2_PS_MASK

#define VTCR_EL2_TG0_MASK	TCR_TG0_MASK

#define VTCR_EL2_TG0_4K		TCR_TG0_4K

#define VTCR_EL2_TG0_16K	TCR_TG0_16K

#define VTCR_EL2_TG0_64K	TCR_TG0_64K

#define VTCR_EL2_SH0_MASK	TCR_SH0_MASK

#define VTCR_EL2_SH0_INNER	TCR_SH0_INNER
@@ -139,7 +140,7 @@ 
 * (see hyp-init.S).

 *

 * Note that when using 4K pages, we concatenate two first level page tables

 * together.

 * together. With 16K pages, we concatenate 16 first level page tables.

 *

 * The magic numbers used for VTTBR_X in this patch can be found in Tables

 * D4-23 and D4-25 in ARM DDI 0487A.b.
@@ -157,7 +158,15 @@ 
 */

#define VTCR_EL2_TGRAN_FLAGS		(VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1)

#define VTTBR_X_TGRAN_MAGIC		38

#else

#elif defined(CONFIG_ARM64_16K_PAGES)

/*

 * Stage2 translation configuration:

 * 16kB pages (TG0 = 2)

 * 2 level page tables (SL = 1)

 */

#define VTCR_EL2_TGRAN_FLAGS		(VTCR_EL2_TG0_16K | VTCR_EL2_SL0_LVL1)

#define VTTBR_X_TGRAN_MAGIC		42

#else	/* 4K */

/*

 * Stage2 translation configuration:

 * 4kB pages (TG0 = 0)

arch/arm64/kvm/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ config KVM_ARM_VGIC_V3 
config KVM

	bool "Kernel-based Virtual Machine (KVM) support"

	depends on OF

	depends on !ARM64_16K_PAGES

	select MMU_NOTIFIER

	select PREEMPT_NOTIFIERS

	select ANON_INODES