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Commit 017636cc authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Disable LP1+ watermarks safely in init 



ILK doesn't like if we just write the LP1+ watermarks registers with 0.
We need to just disable the watermarks by clearing the enable bit. Use
that method also when disabling LP1+ watermarks in init_clock_gating.

It looks like disabling the sprite LP1 watermarks can cause underruns
even if we just toggle the WM1S_LP_EN bit. So treat that bit like the
actual watermark numbers and avoid setting it to 0 immediately.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ce0e0713

drivers/gpu/drm/i915/intel_pm.c

+19 −12
Original line number Diff line number Diff line
@@ -5051,6 +5051,20 @@ static void g4x_disable_trickle_feed(struct drm_device *dev) 
	}

}



static void ilk_init_lp_watermarks(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);

	I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);

	I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);



	/*

	 * Don't touch WM1S_LP_EN here.

	 * Doing so could cause underruns.

	 */

}



static void ironlake_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5084,9 +5098,8 @@ static void ironlake_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(DISP_ARB_CTL,

		   (I915_READ(DISP_ARB_CTL) |

		    DISP_FBC_WM_DIS));

	I915_WRITE(WM3_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);



	ilk_init_lp_watermarks(dev);



	/*

	 * Based on the document from hardware guys the following bits
@@ -5193,9 +5206,7 @@ static void gen6_init_clock_gating(struct drm_device *dev) 
		I915_WRITE(GEN6_GT_MODE,

			   _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));



	I915_WRITE(WM3_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);

	ilk_init_lp_watermarks(dev);



	I915_WRITE(CACHE_MODE_0,

		   _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
@@ -5369,9 +5380,7 @@ static void haswell_init_clock_gating(struct drm_device *dev) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;



	I915_WRITE(WM3_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);

	ilk_init_lp_watermarks(dev);



	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.

	 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
@@ -5420,9 +5429,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t snpcr;



	I915_WRITE(WM3_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);

	ilk_init_lp_watermarks(dev);



	I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);