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Commit 0160f055 authored by Arun Siluvery's avatar Arun Siluvery Committed by Daniel Vetter
Browse files

drm/i915/gen8: Add WaClearSlmSpaceAtContextSwitch workaround 



In Indirect context w/a batch buffer,
WaClearSlmSpaceAtContextSwitch

This WA performs writes to scratch page so it must be valid, this check
is performed before initializing the batch with this WA.

v2: s/PIPE_CONTROL_FLUSH_RO_CACHES/PIPE_CONTROL_FLUSH_L3 (Ville)

v3: GTT bit in scratch address should be mbz (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: default avatarRafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 9fb73863

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -415,6 +415,7 @@ 
#define   DISPLAY_PLANE_A           (0<<20)

#define   DISPLAY_PLANE_B           (1<<20)

#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))

#define   PIPE_CONTROL_FLUSH_L3				(1<<27)

#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */

#define   PIPE_CONTROL_MMIO_WRITE			(1<<23)

#define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)

drivers/gpu/drm/i915/intel_lrc.c

+15 −0
Original line number Diff line number Diff line
@@ -1147,6 +1147,7 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, 
				    uint32_t *const batch,

				    uint32_t *offset)

{

	uint32_t scratch_addr;

	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);



	/* WaDisableCtxRestoreArbitration:bdw,chv */
@@ -1175,6 +1176,20 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, 
		wa_ctx_emit(batch, l3sqc4_flush & ~GEN8_LQSC_FLUSH_COHERENT_LINES);

	}



	/* WaClearSlmSpaceAtContextSwitch:bdw,chv */

	/* Actual scratch location is at 128 bytes offset */

	scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES;



	wa_ctx_emit(batch, GFX_OP_PIPE_CONTROL(6));

	wa_ctx_emit(batch, (PIPE_CONTROL_FLUSH_L3 |

			    PIPE_CONTROL_GLOBAL_GTT_IVB |

			    PIPE_CONTROL_CS_STALL |

			    PIPE_CONTROL_QW_WRITE));

	wa_ctx_emit(batch, scratch_addr);

	wa_ctx_emit(batch, 0);

	wa_ctx_emit(batch, 0);

	wa_ctx_emit(batch, 0);



	/* Pad to end of cacheline */

	while (index % CACHELINE_DWORDS)

		wa_ctx_emit(batch, MI_NOOP);