Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 01322341 authored by Kever Yang's avatar Kever Yang Committed by Heiko Stuebner
Browse files

clk: rockchip: fix rk3288 clk_usbphy480m_gate bit location in register 



According to rk3288 trm, the clk_usbphy480m_gate is located at
bit 14 of CRU_CLKGATE5_CON register.

Signed-off-by: default avatarKever Yang <kever.yang@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 9aa75e6e

drivers/clk/rockchip/clk-rk3288.c

+1 −1
Original line number Diff line number Diff line
@@ -588,7 +588,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { 


	COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0,

			RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,

			RK3288_CLKGATE_CON(5), 15, GFLAGS),

			RK3288_CLKGATE_CON(5), 14, GFLAGS),

	COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,

			RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,

			RK3288_CLKGATE_CON(3), 6, GFLAGS),