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Commit 01188858 authored by Ben Wright's avatar Ben Wright Committed by Greg Kroah-Hartman
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Staging: bcm: Macros: Fixed multiple coding style violations. 



Fixed multiple indentation issues.

Signed-off-by: default avatarBenjamin James Wright <bwright.au@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent e5969d55

drivers/staging/bcm/Macros.h

+167 −170
Original line number Diff line number Diff line
@@ -4,9 +4,9 @@ 
#ifndef __MACROS_H__

#define __MACROS_H__



#define TX_TIMER_PERIOD 10	//10 msec

#define TX_TIMER_PERIOD 10 /*10 msec*/

#define MAX_CLASSIFIERS 100

//#define MAX_CLASSIFIERS_PER_SF  20

/* #define MAX_CLASSIFIERS_PER_SF  20 */

#define MAX_TARGET_DSX_BUFFERS 24



#define MAX_CNTRL_PKTS    100
@@ -20,20 +20,20 @@ 
#define MAC_ADDR_REGISTER 0xbf60d000





///////////Quality of Service///////////////////////////

/* Quality of Service */

#define NO_OF_QUEUES 17

#define HiPriority                  NO_OF_QUEUES-1

#define HiPriority (NO_OF_QUEUES-1)

#define LowPriority 0

#define BE          2

#define rtPS        4

#define ERTPS       5

#define UGS         6



#define BE_BUCKET_SIZE          	1024*1024*100  //32kb

#define rtPS_BUCKET_SIZE        	1024*1024*100    //8kb

#define MAX_ALLOWED_RATE    		1024*1024*100

#define BE_BUCKET_SIZE       (1024*1024*100)  /* 32kb */

#define rtPS_BUCKET_SIZE     (1024*1024*100) /*  8kb */

#define MAX_ALLOWED_RATE     (1024*1024*100)

#define TX_PACKET_THRESHOLD  10

#define XSECONDS                    1*HZ

#define XSECONDS             (1*HZ)

#define DSC_ACTIVATE_REQUEST 248

#define QUEUE_DEPTH_OFFSET   0x1fc01000

#define MAX_DEVICE_DESC_SIZE 2040
@@ -54,7 +54,7 @@ 
#define IP_PACKET_ONLY_MODE       0

#define ETH_PACKET_TUNNELING_MODE 1



////////////Link Request//////////////

/* Link Request */

#define SET_MAC_ADDRESS_REQUEST 0

#define SYNC_UP_REQUEST         1

#define SYNCED_UP               2
@@ -111,11 +111,11 @@ 
#define LEADER_SIZE           sizeof(LEADER)

#define MAC_ADDR_REQ_SIZE     sizeof(PACKETTOSEND)

#define SS_INFO_REQ_SIZE      sizeof(PACKETTOSEND)

#define	CM_REQUEST_SIZE					LEADER_SIZE + sizeof(stLocalSFChangeRequest)

#define CM_REQUEST_SIZE       (LEADER_SIZE + sizeof(stLocalSFChangeRequest))

#define IDLE_REQ_SIZE         sizeof(PACKETTOSEND)





#define MAX_TRANSFER_CTRL_BYTE_USB		2 * 1024

#define MAX_TRANSFER_CTRL_BYTE_USB (2*1024)



#define GET_MAILBOX1_REG_REQUEST        0x87

#define GET_MAILBOX1_REG_RESPONSE       0x67
@@ -147,10 +147,10 @@ 
#define CM_INDICATION   6

#define PARAM_RESP      7

#define BUFFER_1K       1024

#define BUFFER_2K 			BUFFER_1K*2

#define BUFFER_4K 			BUFFER_2K*2

#define BUFFER_8K 			BUFFER_4K*2

#define BUFFER_16K 			BUFFER_8K*2

#define BUFFER_2K       (BUFFER_1K*2)

#define BUFFER_4K       (BUFFER_2K*2)

#define BUFFER_8K       (BUFFER_4K*2)

#define BUFFER_16K      (BUFFER_8K*2)

#define DOWNLINK_DIR    0

#define UPLINK_DIR      1
@@ -183,8 +183,7 @@ enum enLinkStatus { 
	COMPLETE_WAKE_UP_NOTIFICATION_FRM_FW = 9

};



typedef enum _E_PHS_DSC_ACTION

{

typedef enum _E_PHS_DSC_ACTION {

	eAddPHSRule = 0,

	eSetPHSRule,

	eDeletePHSRule,
@@ -192,9 +191,9 @@ typedef enum _E_PHS_DSC_ACTION 
} E_PHS_DSC_ACTION;





#define CM_CONTROL_NEWDSX_MULTICLASSIFIER_REQ		0x89    // Host to Mac

#define CM_CONTROL_NEWDSX_MULTICLASSIFIER_RESP      0xA9    // Mac to Host

#define MASK_DISABLE_HEADER_SUPPRESSION 			0x10 //0b000010000

#define CM_CONTROL_NEWDSX_MULTICLASSIFIER_REQ  0x89 /* Host to Mac */

#define CM_CONTROL_NEWDSX_MULTICLASSIFIER_RESP 0xA9 /* Mac to Host */

#define MASK_DISABLE_HEADER_SUPPRESSION        0x10 /* 0b000010000 */

#define MINIMUM_PENDING_DESCRIPTORS            5



#define SHUTDOWN_HOSTINITIATED_REQUESTPAYLOAD 0xCC
@@ -263,15 +262,15 @@ typedef enum _E_PHS_DSC_ACTION 


#define INVALID_QUEUE_INDEX NO_OF_QUEUES



#define INVALID_PID (pid_t)-1

#define INVALID_PID ((pid_t)-1)

#define DDR_80_MHZ  0

#define DDR_100_MHZ 1

#define DDR_120_MHZ    	2 //  Additional Frequency for T3LP

#define DDR_120_MHZ 2 /* Additional Frequency for T3LP */

#define DDR_133_MHZ 3

#define DDR_140_MHZ    	4 //  Not Used (Reserved for future)

#define DDR_160_MHZ    	5 //  Additional Frequency for T3LP

#define DDR_180_MHZ    	6 //  Not Used (Reserved for future)

#define DDR_200_MHZ    	7 //  Not Used (Reserved for future)

#define DDR_140_MHZ 4 /* Not Used (Reserved for future) */

#define DDR_160_MHZ 5 /* Additional Frequency for T3LP  */

#define DDR_180_MHZ 6 /* Not Used (Reserved for future) */

#define DDR_200_MHZ 7 /* Not Used (Reserved for future) */



#define MIPS_200_MHZ   0

#define MIPS_160_MHZ   1
@@ -311,7 +310,7 @@ typedef enum _E_PHS_DSC_ACTION 
#define CHIP_ID_REG             0x0F000000

#define GPIO_MODE_REG           0x0F000034

#define GPIO_OUTPUT_REG         0x0F00003C

#define WIMAX_MAX_ALLOWED_RATE  1024*1024*50

#define WIMAX_MAX_ALLOWED_RATE  (1024*1024*50)



#define T3 0xbece0300

#define TARGET_SFID_TXDESC_MAP_LOC 0xBFFFF400
@@ -330,16 +329,14 @@ typedef enum _E_PHS_DSC_ACTION 
#define HPM_CONFIG_MSW    0x0F000D58



#define T3B 0xbece0310

typedef enum eNVM_TYPE

{

typedef enum eNVM_TYPE {

	NVM_AUTODETECT = 0,

	NVM_EEPROM,

	NVM_FLASH,

	NVM_UNKNOWN

} NVM_TYPE;



typedef enum ePMU_MODES

{

typedef enum ePMU_MODES {

	HYBRID_MODE_7C  = 0,

	INTERNAL_MODE_6 = 1,

	HYBRID_MODE_6   = 2
@@ -360,4 +357,4 @@ enum eAbortPattern { 
#define SKB_CB_LATENCY_OFFSET           1

#define SKB_CB_TCPACK_OFFSET            2



#endif	//__MACROS_H__
 
#endif /* __MACROS_H__ */