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Commit 00bb09c4 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2017-10-04' of... 

Merge tag 'drm-intel-fixes-2017-10-04' of git://anongit.freedesktop.org/git/drm-intel into drm-fixes

drm/i915 fixes for 4.14-rc4:

All 3 highest GLK bugs fixed by Imre:
- GLK drv reload - Fix DDI Phy init if it was already on.
- GLK suspend resume - Reprogram DMC firmware after s3/s4.
- GLK DC states - Fix idleness calculation.

* tag 'drm-intel-fixes-2017-10-04' of git://anongit.freedesktop.org/git/drm-intel:
  drm/i915/glk: Fix DMC/DC state idleness calculation
  drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume
  drm/i915: Fix DDI PHY init if it was already on
parents 1b0e19bb 069d40f5

drivers/gpu/drm/i915/intel_csr.c

+1 −1
Original line number Diff line number Diff line
@@ -216,7 +216,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) 


	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;



	if (IS_BROXTON(dev_priv))

	if (IS_GEN9_LP(dev_priv))

		mask |= DC_STATE_DEBUG_MASK_CORES;



	/* The below bit doesn't need to be cleared ever afterwards */

drivers/gpu/drm/i915/intel_ddi.c

+2 −1
Original line number Diff line number Diff line
@@ -1655,7 +1655,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 
out:

	if (ret && IS_GEN9_LP(dev_priv)) {

		tmp = I915_READ(BXT_PHY_CTL(port));

		if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |

		if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |

			    BXT_PHY_LANE_POWERDOWN_ACK |

			    BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)

			DRM_ERROR("Port %c enabled but PHY powered down? "

				  "(PHY_CTL %08x)\n", port_name(port), tmp);

drivers/gpu/drm/i915/intel_dpio_phy.c

+0 −20
Original line number Diff line number Diff line
@@ -208,12 +208,6 @@ static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = { 
	},

};



static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)

{

	return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |

		BIT(phy_info->channel[DPIO_CH0].port);

}



static const struct bxt_ddi_phy_info *

bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)

{
@@ -313,7 +307,6 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, 
			    enum dpio_phy phy)

{

	const struct bxt_ddi_phy_info *phy_info;

	enum port port;



	phy_info = bxt_get_phy_info(dev_priv, phy);
@@ -335,19 +328,6 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, 
		return false;

	}



	for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {

		u32 tmp = I915_READ(BXT_PHY_CTL(port));



		if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {

			DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "

					 "for port %c powered down "

					 "(PHY_CTL %08x)\n",

					 phy, port_name(port), tmp);



			return false;

		}

	}



	return true;

}

drivers/gpu/drm/i915/intel_runtime_pm.c

+3 −0
Original line number Diff line number Diff line
@@ -2782,6 +2782,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume 


	/* 6. Enable DBUF */

	gen9_dbuf_enable(dev_priv);



	if (resume && dev_priv->csr.dmc_payload)

		intel_csr_load_program(dev_priv);

}



#undef CNL_PROCMON_IDX