drm/i915: kick out cmd_parser specific structs from i915_drv.h (007873b3) · Commits · e / devices / android_kernel_teracube_emerald

drivers/gpu/drm/i915/i915_cmd_parser.c

+96 −0

Original line number	Diff line number	Diff line
		@@ -86,6 +86,102 @@
		* general bitmasking mechanism.
		*/

		/*
		* A command that requires special handling by the command parser.
		*/
		struct drm_i915_cmd_descriptor {
		/*
		* Flags describing how the command parser processes the command.
		*
		* CMD_DESC_FIXED: The command has a fixed length if this is set,
		* a length mask if not set
		* CMD_DESC_SKIP: The command is allowed but does not follow the
		* standard length encoding for the opcode range in
		* which it falls
		* CMD_DESC_REJECT: The command is never allowed
		* CMD_DESC_REGISTER: The command should be checked against the
		* register whitelist for the appropriate ring
		* CMD_DESC_MASTER: The command is allowed if the submitting process
		* is the DRM master
		*/
		u32 flags;
		#define CMD_DESC_FIXED (1<<0)
		#define CMD_DESC_SKIP (1<<1)
		#define CMD_DESC_REJECT (1<<2)
		#define CMD_DESC_REGISTER (1<<3)
		#define CMD_DESC_BITMASK (1<<4)
		#define CMD_DESC_MASTER (1<<5)

		/*
		* The command's unique identification bits and the bitmask to get them.
		* This isn't strictly the opcode field as defined in the spec and may
		* also include type, subtype, and/or subop fields.
		*/
		struct {
		u32 value;
		u32 mask;
		} cmd;

		/*
		* The command's length. The command is either fixed length (i.e. does
		* not include a length field) or has a length field mask. The flag
		* CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
		* a length mask. All command entries in a command table must include
		* length information.
		*/
		union {
		u32 fixed;
		u32 mask;
		} length;

		/*
		* Describes where to find a register address in the command to check
		* against the ring's register whitelist. Only valid if flags has the
		* CMD_DESC_REGISTER bit set.
		*
		* A non-zero step value implies that the command may access multiple
		* registers in sequence (e.g. LRI), in that case step gives the
		* distance in dwords between individual offset fields.
		*/
		struct {
		u32 offset;
		u32 mask;
		u32 step;
		} reg;

		#define MAX_CMD_DESC_BITMASKS 3
		/*
		* Describes command checks where a particular dword is masked and
		* compared against an expected value. If the command does not match
		* the expected value, the parser rejects it. Only valid if flags has
		* the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
		* are valid.
		*
		* If the check specifies a non-zero condition_mask then the parser
		* only performs the check when the bits specified by condition_mask
		* are non-zero.
		*/
		struct {
		u32 offset;
		u32 mask;
		u32 expected;
		u32 condition_offset;
		u32 condition_mask;
		} bits[MAX_CMD_DESC_BITMASKS];
		};

		/*
		* A table of commands requiring special handling by the command parser.
		*
		* Each engine has an array of tables. Each table consists of an array of
		* command descriptors, which must be sorted with command opcodes in
		* ascending order.
		*/
		struct drm_i915_cmd_table {
		const struct drm_i915_cmd_descriptor *table;
		int count;
		};

		#define STD_MI_OPCODE_SHIFT (32 - 9)
		#define STD_3D_OPCODE_SHIFT (32 - 16)
		#define STD_2D_OPCODE_SHIFT (32 - 10)

drivers/gpu/drm/i915/i915_drv.h

+0 −96

Original line number	Diff line number	Diff line
		@@ -2454,102 +2454,6 @@ static inline struct scatterlist __sg_next(struct scatterlist sg)
		(((__iter).curr += PAGE_SIZE) < (__iter).max) \|\| \
		((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))

		/*
		* A command that requires special handling by the command parser.
		*/
		struct drm_i915_cmd_descriptor {
		/*
		* Flags describing how the command parser processes the command.
		*
		* CMD_DESC_FIXED: The command has a fixed length if this is set,
		* a length mask if not set
		* CMD_DESC_SKIP: The command is allowed but does not follow the
		* standard length encoding for the opcode range in
		* which it falls
		* CMD_DESC_REJECT: The command is never allowed
		* CMD_DESC_REGISTER: The command should be checked against the
		* register whitelist for the appropriate ring
		* CMD_DESC_MASTER: The command is allowed if the submitting process
		* is the DRM master
		*/
		u32 flags;
		#define CMD_DESC_FIXED (1<<0)
		#define CMD_DESC_SKIP (1<<1)
		#define CMD_DESC_REJECT (1<<2)
		#define CMD_DESC_REGISTER (1<<3)
		#define CMD_DESC_BITMASK (1<<4)
		#define CMD_DESC_MASTER (1<<5)

		/*
		* The command's unique identification bits and the bitmask to get them.
		* This isn't strictly the opcode field as defined in the spec and may
		* also include type, subtype, and/or subop fields.
		*/
		struct {
		u32 value;
		u32 mask;
		} cmd;

		/*
		* The command's length. The command is either fixed length (i.e. does
		* not include a length field) or has a length field mask. The flag
		* CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
		* a length mask. All command entries in a command table must include
		* length information.
		*/
		union {
		u32 fixed;
		u32 mask;
		} length;

		/*
		* Describes where to find a register address in the command to check
		* against the ring's register whitelist. Only valid if flags has the
		* CMD_DESC_REGISTER bit set.
		*
		* A non-zero step value implies that the command may access multiple
		* registers in sequence (e.g. LRI), in that case step gives the
		* distance in dwords between individual offset fields.
		*/
		struct {
		u32 offset;
		u32 mask;
		u32 step;
		} reg;

		#define MAX_CMD_DESC_BITMASKS 3
		/*
		* Describes command checks where a particular dword is masked and
		* compared against an expected value. If the command does not match
		* the expected value, the parser rejects it. Only valid if flags has
		* the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
		* are valid.
		*
		* If the check specifies a non-zero condition_mask then the parser
		* only performs the check when the bits specified by condition_mask
		* are non-zero.
		*/
		struct {
		u32 offset;
		u32 mask;
		u32 expected;
		u32 condition_offset;
		u32 condition_mask;
		} bits[MAX_CMD_DESC_BITMASKS];
		};

		/*
		* A table of commands requiring special handling by the command parser.
		*
		* Each engine has an array of tables. Each table consists of an array of
		* command descriptors, which must be sorted with command opcodes in
		* ascending order.
		*/
		struct drm_i915_cmd_table {
		const struct drm_i915_cmd_descriptor *table;
		int count;
		};

		static inline const struct intel_device_info *
		intel_info(const struct drm_i915_private *dev_priv)
		{