Commit 006dfb3c authored May 19, 2013 by Vineet Gupta

ARC: Use enough bits for determining page's cache color



The current code uses 2 bits for determining page's dcache color, thus
sorting pages into 4 bins, whereas the aliasing dcache really has 2 bins
(8k page, 64k dcache - 4 way-set-assoc).
This can cause extraneous flushes - e.g. color 0 and 2.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

parent 3e87974d

arch/arc/include/asm/cacheflush.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -93,7 +93,7 @@ static inline int cache_is_vipt_aliasing(void)
		#endif
		}

		#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 3)
		#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 1)

		/*
		* checks if two addresses (after page aligning) index into same cache set