Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 005510ae authored by Thierry Reding's avatar Thierry Reding
Browse files

Merge branch 'for-3.20/soc' into for-3.20/arm64

parents 97bf6af1 3568df3d

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt

+26 −0
Original line number Original line Diff line number Diff line
@@ -47,6 +47,23 @@ Required properties when nvidia,suspend-mode=<0>: 
  sleep mode, the warm boot code will restore some PLLs, clocks and then

  sleep mode, the warm boot code will restore some PLLs, clocks and then

  bring up CPU0 for resuming the system.

  bring up CPU0 for resuming the system.





Hardware-triggered thermal reset:

On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,

hardware-triggered thermal reset will be enabled.



Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):

- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are

                             described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the

                             Tegra K1 Technical Reference Manual.

- nvidia,bus-addr : Bus address of the PMU on the I2C bus

- nvidia,reg-addr : I2C register address to write poweroff command to

- nvidia,reg-data : Poweroff command to write to PMU



Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):

- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.

                     Defaults to 0. Valid values are described in section 12.5.2

                     "Pinmux Support" of the Tegra4 Technical Reference Manual.



Example:

Example:





/ SoC dts including file

/ SoC dts including file
@@ -68,6 +85,15 @@ pmc@7000f400 { 




/ Tegra board dts file

/ Tegra board dts file

{

{

	...

	pmc@7000f400 {

		i2c-thermtrip {

			nvidia,i2c-controller-id = <4>;

			nvidia,bus-addr = <0x40>;

			nvidia,reg-addr = <0x36>;

			nvidia,reg-data = <0x2>;

		};

	};

	...

	...

	clocks {

	clocks {

		compatible = "simple-bus";

		compatible = "simple-bus";

arch/arm/boot/dts/tegra124-jetson-tk1.dts

+7 −0
Original line number Original line Diff line number Diff line
@@ -1673,6 +1673,13 @@ 
		nvidia,core-pwr-off-time = <61036>;

		nvidia,core-pwr-off-time = <61036>;

		nvidia,core-power-req-active-high;

		nvidia,core-power-req-active-high;

		nvidia,sys-clock-req-active-high;

		nvidia,sys-clock-req-active-high;



		i2c-thermtrip {

			nvidia,i2c-controller-id = <4>;

			nvidia,bus-addr = <0x40>;

			nvidia,reg-addr = <0x36>;

			nvidia,reg-data = <0x2>;

		};

	};

	};





	/* Serial ATA */

	/* Serial ATA */

arch/arm/mach-tegra/Kconfig

+4 −0
Original line number Original line Diff line number Diff line
@@ -27,6 +27,7 @@ config ARCH_TEGRA_2x_SOC 
	select PINCTRL_TEGRA20

	select PINCTRL_TEGRA20

	select PL310_ERRATA_727915 if CACHE_L2X0

	select PL310_ERRATA_727915 if CACHE_L2X0

	select PL310_ERRATA_769419 if CACHE_L2X0

	select PL310_ERRATA_769419 if CACHE_L2X0

	select TEGRA_TIMER

	help

	help

	  Support for NVIDIA Tegra AP20 and T20 processors, based on the

	  Support for NVIDIA Tegra AP20 and T20 processors, based on the

	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller

	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -37,6 +38,7 @@ config ARCH_TEGRA_3x_SOC 
	select ARM_ERRATA_764369 if SMP

	select ARM_ERRATA_764369 if SMP

	select PINCTRL_TEGRA30

	select PINCTRL_TEGRA30

	select PL310_ERRATA_769419 if CACHE_L2X0

	select PL310_ERRATA_769419 if CACHE_L2X0

	select TEGRA_TIMER

	help

	help

	  Support for NVIDIA Tegra T30 processor family, based on the

	  Support for NVIDIA Tegra T30 processor family, based on the

	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller

	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -47,6 +49,7 @@ config ARCH_TEGRA_114_SOC 
	select ARM_L1_CACHE_SHIFT_6

	select ARM_L1_CACHE_SHIFT_6

	select HAVE_ARM_ARCH_TIMER

	select HAVE_ARM_ARCH_TIMER

	select PINCTRL_TEGRA114

	select PINCTRL_TEGRA114

	select TEGRA_TIMER

	help

	help

	  Support for NVIDIA Tegra T114 processor family, based on the

	  Support for NVIDIA Tegra T114 processor family, based on the

	  ARM CortexA15MP CPU

	  ARM CortexA15MP CPU
@@ -56,6 +59,7 @@ config ARCH_TEGRA_124_SOC 
	select ARM_L1_CACHE_SHIFT_6

	select ARM_L1_CACHE_SHIFT_6

	select HAVE_ARM_ARCH_TIMER

	select HAVE_ARM_ARCH_TIMER

	select PINCTRL_TEGRA124

	select PINCTRL_TEGRA124

	select TEGRA_TIMER

	help

	help

	  Support for NVIDIA Tegra T124 processor family, based on the

	  Support for NVIDIA Tegra T124 processor family, based on the

	  ARM CortexA15MP CPU

	  ARM CortexA15MP CPU

drivers/clocksource/Kconfig

+3 −0
Original line number Original line Diff line number Diff line
@@ -47,6 +47,9 @@ config SUN5I_HSTIMER 
	select CLKSRC_MMIO

	select CLKSRC_MMIO

	bool

	bool





config TEGRA_TIMER

	bool



config VT8500_TIMER

config VT8500_TIMER

	bool

	bool

drivers/clocksource/Makefile

+1 −1
Original line number Original line Diff line number Diff line
@@ -27,7 +27,7 @@ obj-$(CONFIG_ARCH_U300) += timer-u300.o 
obj-$(CONFIG_SUN4I_TIMER)	+= sun4i_timer.o

obj-$(CONFIG_SUN4I_TIMER)	+= sun4i_timer.o

obj-$(CONFIG_SUN5I_HSTIMER)	+= timer-sun5i.o

obj-$(CONFIG_SUN5I_HSTIMER)	+= timer-sun5i.o

obj-$(CONFIG_MESON6_TIMER)	+= meson6_timer.o

obj-$(CONFIG_MESON6_TIMER)	+= meson6_timer.o

obj-$(CONFIG_ARCH_TEGRA)	+= tegra20_timer.o

obj-$(CONFIG_TEGRA_TIMER)	+= tegra20_timer.o

obj-$(CONFIG_VT8500_TIMER)	+= vt8500_timer.o

obj-$(CONFIG_VT8500_TIMER)	+= vt8500_timer.o

obj-$(CONFIG_ARCH_NSPIRE)	+= zevio-timer.o

obj-$(CONFIG_ARCH_NSPIRE)	+= zevio-timer.o

obj-$(CONFIG_ARCH_BCM_MOBILE)	+= bcm_kona_timer.o

obj-$(CONFIG_ARCH_BCM_MOBILE)	+= bcm_kona_timer.o