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Commit fffae950 authored by Simon Horman's avatar Simon Horman
Browse files

Merge tag 'clk-renesas-for-v4.8-tag2' into HEAD 

clk: renesas: Updates for v4.8 (take two)

  - Add support for R-Car V2H,
  - Add FDP1, DRIF, and thermal clocks on R-Car H3,
  - Correct a wrong parent clock.
parents 21cc405c e4c82863

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

+4 −3
Original line number Diff line number Diff line
@@ -13,7 +13,8 @@ They provide the following functionalities: 


Required Properties:

  - compatible: Must be one of:

      - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC

      - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)

      - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)



  - reg: Base address and length of the memory resource used by the CPG/MSSR

    block
@@ -21,8 +22,8 @@ Required Properties: 
  - clocks: References to external parent clocks, one entry for each entry in

    clock-names

  - clock-names: List of external parent clock names. Valid names are:

      - "extal" (r8a7795)

      - "extalr" (r8a7795)

      - "extal" (r8a7795, r8a7796)

      - "extalr" (r8a7795, r8a7796)



  - #clock-cells: Must be 2

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ Required Properties: 
    - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks

    - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks

    - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks

    - "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks

    - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks

    - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks

    - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks

Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ Required Properties: 
  - compatible: Must be one of

    - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG

    - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG

    - "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG

    - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG

    - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG

    and "renesas,rcar-gen2-cpg-clocks" as a fallback.

drivers/clk/renesas/Kconfig

+2 −0
Original line number Diff line number Diff line 
config CLK_RENESAS_CPG_MSSR

	bool

	default y if ARCH_R8A7795

	default y if ARCH_R8A7796



config CLK_RENESAS_CPG_MSTP

	bool
@@ -11,6 +12,7 @@ config CLK_RENESAS_CPG_MSTP 
	default y if ARCH_R8A7779

	default y if ARCH_R8A7790

	default y if ARCH_R8A7791

	default y if ARCH_R8A7792

	default y if ARCH_R8A7793

	default y if ARCH_R8A7794

	default y if ARCH_SH73A0

drivers/clk/renesas/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -6,9 +6,11 @@ obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o 
obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o

obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o clk-div6.o

obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o clk-div6.o

obj-$(CONFIG_ARCH_R8A7792)		+= clk-rcar-gen2.o clk-div6.o

obj-$(CONFIG_ARCH_R8A7793)		+= clk-rcar-gen2.o clk-div6.o

obj-$(CONFIG_ARCH_R8A7794)		+= clk-rcar-gen2.o clk-div6.o

obj-$(CONFIG_ARCH_R8A7795)		+= r8a7795-cpg-mssr.o

obj-$(CONFIG_ARCH_R8A7795)		+= r8a7795-cpg-mssr.o rcar-gen3-cpg.o

obj-$(CONFIG_ARCH_R8A7796)		+= r8a7796-cpg-mssr.o rcar-gen3-cpg.o

obj-$(CONFIG_ARCH_SH73A0)		+= clk-sh73a0.o clk-div6.o



obj-$(CONFIG_CLK_RENESAS_CPG_MSSR)	+= renesas-cpg-mssr.o clk-div6.o