Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ffdf7862 authored by Russell King's avatar Russell King Committed by Russell King
Browse files

[ARM] pxa: Add PXA3_ prefix to PXA3 specific constants 



standby.S contains both PXA2 and PXA3 specific code.  The PXA3
specific constants clash with the PXA2 ones, so give them a prefix.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 4e5e8de0

arch/arm/mach-pxa/standby.S

+41 −41
Original line number Diff line number Diff line
@@ -35,20 +35,20 @@ ENTRY(pxa_cpu_standby) 


#ifdef CONFIG_PXA3xx



#define MDCNFG		0x0000

#define MDCNFG_DMCEN	(1 << 30)

#define DDR_HCAL	0x0060

#define DDR_HCAL_HCRNG	0x1f

#define DDR_HCAL_HCPROG	(1 << 28)

#define DDR_HCAL_HCEN	(1 << 31)

#define DMCIER		0x0070

#define DMCIER_EDLP	(1 << 29)

#define DMCISR		0x0078

#define RCOMP		0x0100

#define RCOMP_SWEVAL	(1 << 31)

#define PXA3_MDCNFG		0x0000

#define PXA3_MDCNFG_DMCEN	(1 << 30)

#define PXA3_DDR_HCAL		0x0060

#define PXA3_DDR_HCAL_HCRNG	0x1f

#define PXA3_DDR_HCAL_HCPROG	(1 << 28)

#define PXA3_DDR_HCAL_HCEN	(1 << 31)

#define PXA3_DMCIER		0x0070

#define PXA3_DMCIER_EDLP	(1 << 29)

#define PXA3_DMCISR		0x0078

#define PXA3_RCOMP		0x0100

#define PXA3_RCOMP_SWEVAL	(1 << 31)



ENTRY(pm_enter_standby_start)

	mov	r1, #0xf6000000		@ DMEMC_REG_BASE (MDCNFG)

	mov	r1, #0xf6000000			@ DMEMC_REG_BASE (PXA3_MDCNFG)

	add	r1, r1, #0x00100000



	/*
@@ -59,54 +59,54 @@ ENTRY(pm_enter_standby_start) 
	 * This also means that only the dynamic memory controller

	 * can be reliably accessed in the code following standby.

	 */

	ldr	r2, [r1]		@ Dummy read MDCNFG

	ldr	r2, [r1]			@ Dummy read PXA3_MDCNFG



	mcr	p14, 0, r0, c7, c0, 0

	.rept	8

	nop

	.endr



	ldr	r0, [r1, #DDR_HCAL]	@ Clear (and wait for) HCEN

	bic	r0, r0, #DDR_HCAL_HCEN

	str	r0, [r1, #DDR_HCAL]

1:	ldr	r0, [r1, #DDR_HCAL]

	tst	r0, #DDR_HCAL_HCEN

	ldr	r0, [r1, #PXA3_DDR_HCAL]	@ Clear (and wait for) HCEN

	bic	r0, r0, #PXA3_DDR_HCAL_HCEN

	str	r0, [r1, #PXA3_DDR_HCAL]

1:	ldr	r0, [r1, #PXA3_DDR_HCAL]

	tst	r0, #PXA3_DDR_HCAL_HCEN

	bne	1b



	ldr	r0, [r1, #RCOMP]	@ Initiate RCOMP

	orr	r0, r0, #RCOMP_SWEVAL

	str	r0, [r1, #RCOMP]

	ldr	r0, [r1, #PXA3_RCOMP]		@ Initiate RCOMP

	orr	r0, r0, #PXA3_RCOMP_SWEVAL

	str	r0, [r1, #PXA3_RCOMP]



	mov	r0, #~0				@ Clear interrupts

	str	r0, [r1, #DMCISR]

	str	r0, [r1, #PXA3_DMCISR]



	ldr	r0, [r1, #DMCIER]	@ set DMIER[EDLP]

	orr	r0, r0, #DMCIER_EDLP

	str	r0, [r1, #DMCIER]

	ldr	r0, [r1, #PXA3_DMCIER]		@ set DMIER[EDLP]

	orr	r0, r0, #PXA3_DMCIER_EDLP

	str	r0, [r1, #PXA3_DMCIER]



	ldr	r0, [r1, #DDR_HCAL]	@ clear HCRNG, set HCPROG, HCEN

	bic	r0, r0, #DDR_HCAL_HCRNG

	orr	r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG

	str	r0, [r1, #DDR_HCAL]

	ldr	r0, [r1, #PXA3_DDR_HCAL]	@ clear HCRNG, set HCPROG, HCEN

	bic	r0, r0, #PXA3_DDR_HCAL_HCRNG

	orr	r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG

	str	r0, [r1, #PXA3_DDR_HCAL]



1:	ldr	r0, [r1, #DMCISR]

	tst	r0, #DMCIER_EDLP

1:	ldr	r0, [r1, #PXA3_DMCISR]

	tst	r0, #PXA3_DMCIER_EDLP

	beq	1b



	ldr	r0, [r1, #MDCNFG]	@ set MDCNFG[DMCEN]

	orr	r0, r0, #MDCNFG_DMCEN

	str	r0, [r1, #MDCNFG]

1:	ldr	r0, [r1, #MDCNFG]

	tst	r0, #MDCNFG_DMCEN

	ldr	r0, [r1, #PXA3_MDCNFG]		@ set PXA3_MDCNFG[DMCEN]

	orr	r0, r0, #PXA3_MDCNFG_DMCEN

	str	r0, [r1, #PXA3_MDCNFG]

1:	ldr	r0, [r1, #PXA3_MDCNFG]

	tst	r0, #PXA3_MDCNFG_DMCEN

	beq	1b



	ldr	r0, [r1, #DDR_HCAL]	@ set DDR_HCAL[HCRNG]

	ldr	r0, [r1, #PXA3_DDR_HCAL]	@ set PXA3_DDR_HCAL[HCRNG]

	orr	r0, r0, #2 @ HCRNG

	str	r0, [r1, #DDR_HCAL]

	str	r0, [r1, #PXA3_DDR_HCAL]



	ldr	r0, [r1, #DMCIER]	@ Clear the interrupt

	ldr	r0, [r1, #PXA3_DMCIER]		@ Clear the interrupt

	bic	r0, r0, #0x20000000

	str	r0, [r1, #DMCIER]

	str	r0, [r1, #PXA3_DMCIER]



	mov	pc, lr

ENTRY(pm_enter_standby_end)