Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ffd58bd2 authored by Saeed Bishara's avatar Saeed Bishara Committed by Nicolas Pitre
Browse files

[ARM] Kirkwood: add support for PCIe1 



This patch extends the kirkwood's PCIe support up to 2 controllers as in the 6282 devices.

Signed-off-by: default avatarSaeed Bishara <saeed@marvell.com>
Signed-off-by: default avatarNicolas Pitre <nico@fluxnic.net>
parent 35fe2fc4

arch/arm/mach-kirkwood/addr-map.c

+8 −2
Original line number Original line Diff line number Diff line
@@ -31,6 +31,8 @@ 
#define ATTR_DEV_CS0		0x3e

#define ATTR_DEV_CS0		0x3e

#define ATTR_PCIE_IO		0xe0

#define ATTR_PCIE_IO		0xe0

#define ATTR_PCIE_MEM		0xe8

#define ATTR_PCIE_MEM		0xe8

#define ATTR_PCIE1_IO		0xd0

#define ATTR_PCIE1_MEM		0xd8

#define ATTR_SRAM		0x01

#define ATTR_SRAM		0x01





/*

/*
@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void) 
		      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);

		      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);

	setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,

	setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,

		      TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);

		      TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);

	setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,

		      TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);

	setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,

		      TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);





	/*

	/*

	 * Setup window for NAND controller.

	 * Setup window for NAND controller.

	 */

	 */

	setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,

	setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,

		      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);

		      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);





	/*

	/*

	 * Setup window for SRAM.

	 * Setup window for SRAM.

	 */

	 */

	setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,

	setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,

		      TARGET_SRAM, ATTR_SRAM, -1);

		      TARGET_SRAM, ATTR_SRAM, -1);





	/*

	/*

arch/arm/mach-kirkwood/common.c

+20 −1
Original line number Original line Diff line number Diff line
@@ -43,6 +43,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = { 
		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),

		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),

		.length		= KIRKWOOD_PCIE_IO_SIZE,

		.length		= KIRKWOOD_PCIE_IO_SIZE,

		.type		= MT_DEVICE,

		.type		= MT_DEVICE,

	}, {

		.virtual	= KIRKWOOD_PCIE1_IO_VIRT_BASE,

		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),

		.length		= KIRKWOOD_PCIE1_IO_SIZE,

		.type		= MT_DEVICE,

	}, {

	}, {

		.virtual	= KIRKWOOD_REGS_VIRT_BASE,

		.virtual	= KIRKWOOD_REGS_VIRT_BASE,

		.pfn		= __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),

		.pfn		= __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
@@ -960,12 +965,14 @@ void __init kirkwood_init(void) 
static int __init kirkwood_clock_gate(void)

static int __init kirkwood_clock_gate(void)

{

{

	unsigned int curr = readl(CLOCK_GATING_CTRL);

	unsigned int curr = readl(CLOCK_GATING_CTRL);

	u32 dev, rev;





	kirkwood_pcie_id(&dev, &rev);

	printk(KERN_DEBUG "Gating clock of unused units\n");

	printk(KERN_DEBUG "Gating clock of unused units\n");

	printk(KERN_DEBUG "before: 0x%08x\n", curr);

	printk(KERN_DEBUG "before: 0x%08x\n", curr);





	/* Make sure those units are accessible */

	/* Make sure those units are accessible */

	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);

	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);





	/* For SATA: first shutdown the phy */

	/* For SATA: first shutdown the phy */

	if (!(kirkwood_clk_ctrl & CGC_SATA0)) {

	if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
@@ -990,6 +997,18 @@ static int __init kirkwood_clock_gate(void) 
		writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);

		writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);

	}

	}





	/* For PCIe 1: first shutdown the phy */

	if (dev == MV88F6282_DEV_ID) {

		if (!(kirkwood_clk_ctrl & CGC_PEX1)) {

			writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);

			while (1)

				if (readl(PCIE1_STATUS) & 0x1)

					break;

			writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);

		}

	} else  /* keep this bit set for devices that don't have PCIe1 */

		kirkwood_clk_ctrl |= CGC_PEX1;



	/* Now gate clock the required units */

	/* Now gate clock the required units */

	writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);

	writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);

	printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));

	printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));

arch/arm/mach-kirkwood/common.h

+4 −1
Original line number Original line Diff line number Diff line
@@ -18,6 +18,9 @@ struct mvsdio_platform_data; 
struct mtd_partition;

struct mtd_partition;

struct mtd_info;

struct mtd_info;





#define KW_PCIE0	(1 << 0)

#define KW_PCIE1	(1 << 1)



/*

/*

 * Basic Kirkwood init functions used early by machine-setup.

 * Basic Kirkwood init functions used early by machine-setup.

 */

 */
@@ -34,7 +37,7 @@ void kirkwood_ehci_init(void); 
void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);

void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);

void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);

void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);

void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);

void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);

void kirkwood_pcie_init(void);

void kirkwood_pcie_init(unsigned int portmask);

void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);

void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);

void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);

void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);

void kirkwood_spi_init(void);

void kirkwood_spi_init(void);

arch/arm/mach-kirkwood/db88f6281-bp-setup.c

+8 −2
Original line number Original line Diff line number Diff line
@@ -82,9 +82,15 @@ static void __init db88f6281_init(void) 




static int __init db88f6281_pci_init(void)

static int __init db88f6281_pci_init(void)

{

{

	if (machine_is_db88f6281_bp())

	if (machine_is_db88f6281_bp()) {

		kirkwood_pcie_init();

		u32 dev, rev;





		kirkwood_pcie_id(&dev, &rev);

		if (dev == MV88F6282_DEV_ID)

			kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);

		else

			kirkwood_pcie_init(KW_PCIE0);

	}

	return 0;

	return 0;

}

}

subsys_initcall(db88f6281_pci_init);

subsys_initcall(db88f6281_pci_init);

arch/arm/mach-kirkwood/include/mach/bridge-regs.h

+2 −1
Original line number Original line Diff line number Diff line
@@ -59,8 +59,9 @@ 
#define CGC_SATA1		(1 << 15)

#define CGC_SATA1		(1 << 15)

#define CGC_XOR1		(1 << 16)

#define CGC_XOR1		(1 << 16)

#define CGC_CRYPTO		(1 << 17)

#define CGC_CRYPTO		(1 << 17)

#define CGC_PEX1		(1 << 18)

#define CGC_GE1			(1 << 19)

#define CGC_GE1			(1 << 19)

#define CGC_TDM			(1 << 20)

#define CGC_TDM			(1 << 20)

#define CGC_RESERVED		((1 << 18) | (0x6 << 21))

#define CGC_RESERVED		(0x6 << 21)





#endif
 
#endif