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Commit ff9faa8b authored by Robert Richter's avatar Robert Richter
Browse files

x86/oprofile: move common macros to op_x86_model.h 



There are duplicate macro implementations in model specific code. This
patch moves all common macros to op_x86_model.h.

Signed-off-by: default avatarRobert Richter <robert.richter@amd.com>
parent d20f24c6

arch/x86/oprofile/op_model_amd.c

+0 −8
Original line number Diff line number Diff line
@@ -26,22 +26,14 @@ 
#define NUM_COUNTERS 4

#define NUM_CONTROLS 4



#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)

#define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)

#define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)

#define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))



#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)

#define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)

#define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)

#define CTRL_SET_ACTIVE(n) (n |= (1<<22))

#define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))

#define CTRL_CLEAR_LO(x) (x &= (1<<21))

#define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)

#define CTRL_SET_ENABLE(val) (val |= 1<<20)

#define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))

#define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))

#define CTRL_SET_UM(val, m) (val |= (m << 8))

#define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))

#define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))

#define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))

arch/x86/oprofile/op_model_p4.c

+0 −2
Original line number Diff line number Diff line
@@ -366,8 +366,6 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = { 
#define CCCR_OVF_P(cccr) ((cccr) & (1U<<31))

#define CCCR_CLEAR_OVF(cccr) ((cccr) &= (~(1U<<31)))



#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)

#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)

#define CTR_READ(l, h, i) do {rdmsr(p4_counters[(i)].counter_address, (l), (h)); } while (0)

#define CTR_WRITE(l, i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1); } while (0)

#define CTR_OVERFLOW_P(ctr) (!((ctr) & 0x80000000))

arch/x86/oprofile/op_model_ppro.c

+0 −8
Original line number Diff line number Diff line
@@ -26,19 +26,11 @@ 
static int num_counters = 2;

static int counter_width = 32;



#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)

#define CTR_OVERFLOWED(n) (!((n) & (1ULL<<(counter_width-1))))



#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)

#define CTRL_READ(l, h, msrs, c) do {rdmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)

#define CTRL_WRITE(l, h, msrs, c) do {wrmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)

#define CTRL_SET_ACTIVE(n) (n |= (1<<22))

#define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))

#define CTRL_CLEAR(x) (x &= (1<<21))

#define CTRL_SET_ENABLE(val) (val |= 1<<20)

#define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))

#define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))

#define CTRL_SET_UM(val, m) (val |= (m << 8))

#define CTRL_SET_EVENT(val, e) (val |= e)



static u64 *reset_value;

arch/x86/oprofile/op_x86_model.h

+9 −0
Original line number Diff line number Diff line
@@ -11,6 +11,15 @@ 
#ifndef OP_X86_MODEL_H

#define OP_X86_MODEL_H



#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)

#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)

#define CTRL_SET_ACTIVE(n) (n |= (1<<22))

#define CTRL_SET_ENABLE(val) (val |= 1<<20)

#define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))

#define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))

#define CTRL_SET_UM(val, m) (val |= (m << 8))

#define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))



struct op_saved_msr {

	unsigned int high;

	unsigned int low;