Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit feebe91a authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: apply gfx_v8 fixes to gfx_v7 as well 



We never ported that back to CIK, so we could run into VM faults here.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 4ea2efae

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+13 −0
Original line number Diff line number Diff line
@@ -3628,6 +3628,19 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 
					unsigned vm_id, uint64_t pd_addr)

{

	int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);

	uint32_t seq = ring->fence_drv.sync_seq;

	uint64_t addr = ring->fence_drv.gpu_addr;



	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

	amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */

				 WAIT_REG_MEM_FUNCTION(3) | /* equal */

				 WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */

	amdgpu_ring_write(ring, addr & 0xfffffffc);

	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

	amdgpu_ring_write(ring, seq);

	amdgpu_ring_write(ring, 0xffffffff);

	amdgpu_ring_write(ring, 4); /* poll interval */



	if (usepfp) {

		/* synce CE with ME to prevent CE fetch CEIB before context switch done */

		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));