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Commit fde207eb authored by Bill Huang's avatar Bill Huang Committed by Thierry Reding
Browse files

clk: tegra: pll: Add code to handle if resets are supported by PLL 



If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.

Reviewed-by: default avatarBenson Leung <bleung@chromium.org>
Signed-off-by: default avatarBill Huang <bilhuang@nvidia.com>
Signed-off-by: default avatarRhyland Klein <rklein@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 407254da

drivers/clk/tegra/clk-pll.c

+12 −0
Original line number Original line Diff line number Diff line
@@ -311,6 +311,12 @@ static void _clk_pll_enable(struct clk_hw *hw) 
		udelay(2);

		udelay(2);

	}

	}





	if (pll->params->reset_reg) {

		val = pll_readl(pll->params->reset_reg, pll);

		val &= ~BIT(pll->params->reset_bit_idx);

		pll_writel(val, pll->params->reset_reg, pll);

	}



	clk_pll_enable_lock(pll);

	clk_pll_enable_lock(pll);





	val = pll_readl_base(pll);

	val = pll_readl_base(pll);
@@ -343,6 +349,12 @@ static void _clk_pll_disable(struct clk_hw *hw) 
		writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);

		writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);

	}

	}





	if (pll->params->reset_reg) {

		val = pll_readl(pll->params->reset_reg, pll);

		val |= BIT(pll->params->reset_bit_idx);

		pll_writel(val, pll->params->reset_reg, pll);

	}



	if (pll->params->iddq_reg) {

	if (pll->params->iddq_reg) {

		val = pll_readl(pll->params->iddq_reg, pll);

		val = pll_readl(pll->params->iddq_reg, pll);

		val |= BIT(pll->params->iddq_bit_idx);

		val |= BIT(pll->params->iddq_bit_idx);

drivers/clk/tegra/clk.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -176,6 +176,8 @@ struct div_nmp { 
 * @lock_enable_bit_idx:	Bit index to enable PLL lock

 * @lock_enable_bit_idx:	Bit index to enable PLL lock

 * @iddq_reg:			PLL IDDQ register offset

 * @iddq_reg:			PLL IDDQ register offset

 * @iddq_bit_idx:		Bit index to enable PLL IDDQ

 * @iddq_bit_idx:		Bit index to enable PLL IDDQ

 * @reset_reg:			Register offset of where RESET bit is

 * @reset_bit_idx:		Shift of reset bit in reset_reg

 * @sdm_din_reg:		Register offset where SDM settings are

 * @sdm_din_reg:		Register offset where SDM settings are

 * @sdm_din_mask:		Mask of SDM divider bits

 * @sdm_din_mask:		Mask of SDM divider bits

 * @sdm_ctrl_reg:		Register offset where SDM enable is

 * @sdm_ctrl_reg:		Register offset where SDM enable is
@@ -239,6 +241,8 @@ struct tegra_clk_pll_params { 
	u32		lock_enable_bit_idx;

	u32		lock_enable_bit_idx;

	u32		iddq_reg;

	u32		iddq_reg;

	u32		iddq_bit_idx;

	u32		iddq_bit_idx;

	u32		reset_reg;

	u32		reset_bit_idx;

	u32		sdm_din_reg;

	u32		sdm_din_reg;

	u32		sdm_din_mask;

	u32		sdm_din_mask;

	u32		sdm_ctrl_reg;

	u32		sdm_ctrl_reg;