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Commit fb182cf8 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm/arm64: vgic: Allow HW irq to be encoded in LR 



Now that struct vgic_lr supports the LR_HW bit and carries a hwirq
field, we can encode that information into the list registers.

This patch provides implementations for both GICv2 and GICv3.

Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 32d2d801

include/linux/irqchip/arm-gic-v3.h

+3 −0
Original line number Diff line number Diff line
@@ -268,9 +268,12 @@ 


#define ICH_LR_EOI			(1UL << 41)

#define ICH_LR_GROUP			(1UL << 60)

#define ICH_LR_HW			(1UL << 61)

#define ICH_LR_STATE			(3UL << 62)

#define ICH_LR_PENDING_BIT		(1UL << 62)

#define ICH_LR_ACTIVE_BIT		(1UL << 63)

#define ICH_LR_PHYS_ID_SHIFT		32

#define ICH_LR_PHYS_ID_MASK		(0x3ffUL << ICH_LR_PHYS_ID_SHIFT)



#define ICH_MISR_EOI			(1 << 0)

#define ICH_MISR_U			(1 << 1)

include/linux/irqchip/arm-gic.h

+2 −1
Original line number Diff line number Diff line
@@ -71,11 +71,12 @@ 


#define GICH_LR_VIRTUALID		(0x3ff << 0)

#define GICH_LR_PHYSID_CPUID_SHIFT	(10)

#define GICH_LR_PHYSID_CPUID		(7 << GICH_LR_PHYSID_CPUID_SHIFT)

#define GICH_LR_PHYSID_CPUID		(0x3ff << GICH_LR_PHYSID_CPUID_SHIFT)

#define GICH_LR_STATE			(3 << 28)

#define GICH_LR_PENDING_BIT		(1 << 28)

#define GICH_LR_ACTIVE_BIT		(1 << 29)

#define GICH_LR_EOI			(1 << 19)

#define GICH_LR_HW			(1 << 31)



#define GICH_VMCR_CTRL_SHIFT		0

#define GICH_VMCR_CTRL_MASK		(0x21f << GICH_VMCR_CTRL_SHIFT)

virt/kvm/arm/vgic-v2.c

+15 −1
Original line number Diff line number Diff line
@@ -48,6 +48,10 @@ static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr) 
		lr_desc.state |= LR_STATE_ACTIVE;

	if (val & GICH_LR_EOI)

		lr_desc.state |= LR_EOI_INT;

	if (val & GICH_LR_HW) {

		lr_desc.state |= LR_HW;

		lr_desc.hwirq = (val & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT;

	}



	return lr_desc;

}
@@ -55,7 +59,9 @@ static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr) 
static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr,

			   struct vgic_lr lr_desc)

{

	u32 lr_val = (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT) | lr_desc.irq;

	u32 lr_val;



	lr_val = lr_desc.irq;



	if (lr_desc.state & LR_STATE_PENDING)

		lr_val |= GICH_LR_PENDING_BIT;
@@ -64,6 +70,14 @@ static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr, 
	if (lr_desc.state & LR_EOI_INT)

		lr_val |= GICH_LR_EOI;



	if (lr_desc.state & LR_HW) {

		lr_val |= GICH_LR_HW;

		lr_val |= (u32)lr_desc.hwirq << GICH_LR_PHYSID_CPUID_SHIFT;

	}



	if (lr_desc.irq < VGIC_NR_SGIS)

		lr_val |= (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT);



	vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = lr_val;

}

virt/kvm/arm/vgic-v3.c

+18 −3
Original line number Diff line number Diff line
@@ -67,6 +67,10 @@ static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr) 
		lr_desc.state |= LR_STATE_ACTIVE;

	if (val & ICH_LR_EOI)

		lr_desc.state |= LR_EOI_INT;

	if (val & ICH_LR_HW) {

		lr_desc.state |= LR_HW;

		lr_desc.hwirq = (val >> ICH_LR_PHYS_ID_SHIFT) & GENMASK(9, 0);

	}



	return lr_desc;

}
@@ -84,10 +88,17 @@ static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr, 
	 * Eventually we want to make this configurable, so we may revisit

	 * this in the future.

	 */

	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)

	switch (vcpu->kvm->arch.vgic.vgic_model) {

	case KVM_DEV_TYPE_ARM_VGIC_V3:

		lr_val |= ICH_LR_GROUP;

	else

		break;

	case  KVM_DEV_TYPE_ARM_VGIC_V2:

		if (lr_desc.irq < VGIC_NR_SGIS)

			lr_val |= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;

		break;

	default:

		BUG();

	}



	if (lr_desc.state & LR_STATE_PENDING)

		lr_val |= ICH_LR_PENDING_BIT;
@@ -95,6 +106,10 @@ static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr, 
		lr_val |= ICH_LR_ACTIVE_BIT;

	if (lr_desc.state & LR_EOI_INT)

		lr_val |= ICH_LR_EOI;

	if (lr_desc.state & LR_HW) {

		lr_val |= ICH_LR_HW;

		lr_val |= ((u64)lr_desc.hwirq) << ICH_LR_PHYS_ID_SHIFT;

	}



	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[LR_INDEX(lr)] = lr_val;

}