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Commit faf68cdf authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Dinh Nguyen
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ARM: dts: socfpga: add the clk-phase property for sd/mmc clock 



The CIU clock for the SD/MMC should be the sdmmc_clk and not the
sdmmc_free_clk. Also, add the correct phase shift the sdmmc_clk.

Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
parent d07e187c

arch/arm/boot/dts/socfpga_arria10.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -362,6 +362,7 @@ 
						compatible = "altr,socfpga-a10-gate-clk";

						clocks = <&sdmmc_free_clk>;

						clk-gate = <0xC8 5>;

						clk-phase = <0 135>;

					};



					qspi_clk: qspi_clk {
@@ -589,7 +590,7 @@ 
			reg = <0xff808000 0x1000>;

			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;

			fifo-depth = <0x400>;

			clocks = <&l4_mp_clk>, <&sdmmc_free_clk>;

			clocks = <&l4_mp_clk>, <&sdmmc_clk>;

			clock-names = "biu", "ciu";

			status = "disabled";

		};