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Commit faceaf6a authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: cleanup amdgpu_ttm_placement_init 



Make it more clear what this function does. No intendet functional change.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1fdc0b76

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+60 −52
Original line number Diff line number Diff line
@@ -116,87 +116,95 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 


static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,

				      struct ttm_placement *placement,

				      struct ttm_place *placements,

				      struct ttm_place *places,

				      u32 domain, u64 flags)

{

	u32 c = 0, i;



	placement->placement = placements;

	placement->busy_placement = placements;



	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {

		unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT;



		if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&

		    adev->mc.visible_vram_size < adev->mc.real_vram_size) {

			placements[c].fpfn =

				adev->mc.visible_vram_size >> PAGE_SHIFT;

			placements[c++].flags = TTM_PL_FLAG_WC |

			places[c].fpfn = visible_pfn;

			if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)

				places[c].lpfn = visible_pfn;

			else

				places[c].lpfn = 0;

			places[c].flags = TTM_PL_FLAG_WC |

				TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM |

				TTM_PL_FLAG_TOPDOWN;

			c++;

		}

		placements[c].fpfn = 0;

		placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |



		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |

			TTM_PL_FLAG_VRAM;

		if (!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED))

			placements[c - 1].flags |= TTM_PL_FLAG_TOPDOWN;

		if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)

			places[c].lpfn = visible_pfn;

		else

			places[c].flags |= TTM_PL_FLAG_TOPDOWN;

		c++;

	}



	if (domain & AMDGPU_GEM_DOMAIN_GTT) {

		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {

			placements[c].fpfn = 0;

			placements[c++].flags = TTM_PL_FLAG_WC |

				TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;

		} else {

			placements[c].fpfn = 0;

			placements[c++].flags = TTM_PL_FLAG_CACHED |

				TTM_PL_FLAG_TT;

		}

		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_FLAG_TT;

		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)

			places[c].flags |= TTM_PL_FLAG_WC |

				TTM_PL_FLAG_UNCACHED;

		else

			places[c].flags |= TTM_PL_FLAG_CACHED;

		c++;

	}



	if (domain & AMDGPU_GEM_DOMAIN_CPU) {

		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {

			placements[c].fpfn = 0;

			placements[c++].flags = TTM_PL_FLAG_WC |

				TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_UNCACHED;

		} else {

			placements[c].fpfn = 0;

			placements[c++].flags = TTM_PL_FLAG_CACHED |

				TTM_PL_FLAG_SYSTEM;

		}

		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_FLAG_SYSTEM;

		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)

			places[c].flags |= TTM_PL_FLAG_WC |

				TTM_PL_FLAG_UNCACHED;

		else

			places[c].flags |= TTM_PL_FLAG_CACHED;

		c++;

	}



	if (domain & AMDGPU_GEM_DOMAIN_GDS) {

		placements[c].fpfn = 0;

		placements[c++].flags = TTM_PL_FLAG_UNCACHED |

			AMDGPU_PL_FLAG_GDS;

		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;

		c++;

	}



	if (domain & AMDGPU_GEM_DOMAIN_GWS) {

		placements[c].fpfn = 0;

		placements[c++].flags = TTM_PL_FLAG_UNCACHED |

			AMDGPU_PL_FLAG_GWS;

		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;

		c++;

	}



	if (domain & AMDGPU_GEM_DOMAIN_OA) {

		placements[c].fpfn = 0;

		placements[c++].flags = TTM_PL_FLAG_UNCACHED |

			AMDGPU_PL_FLAG_OA;

		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;

		c++;

	}



	if (!c) {

		placements[c].fpfn = 0;

		placements[c++].flags = TTM_PL_MASK_CACHING |

			TTM_PL_FLAG_SYSTEM;

		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;

		c++;

	}



	placement->num_placement = c;

	placement->num_busy_placement = c;

	placement->placement = places;



	for (i = 0; i < c; i++) {

		if ((flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&

			(placements[i].flags & TTM_PL_FLAG_VRAM) &&

			!placements[i].fpfn)

			placements[i].lpfn =

				adev->mc.visible_vram_size >> PAGE_SHIFT;

		else

			placements[i].lpfn = 0;

	}

	placement->num_busy_placement = c;

	placement->busy_placement = places;

}



void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain)