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Commit faadaf97 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'next' of git://people.freedesktop.org/~deathsimple/linux into drm-next 

This merges Christian work that has been hanging around on the list.
parents 6b9d89b4 55d7c221

drivers/gpu/drm/radeon/evergreen.c

+15 −18
Original line number Diff line number Diff line
@@ -1368,7 +1368,15 @@ void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 
	/* set to DX10/11 mode */

	radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));

	radeon_ring_write(ring, 1);

	/* FIXME: implement */



	if (ring->rptr_save_reg) {

		uint32_t next_rptr = ring->wptr + 3 + 4;

		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

		radeon_ring_write(ring, ((ring->rptr_save_reg - 

					  PACKET3_SET_CONFIG_REG_START) >> 2));

		radeon_ring_write(ring, next_rptr);

	}



	radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

	radeon_ring_write(ring,

#ifdef __BIG_ENDIAN
@@ -3087,13 +3095,11 @@ static int evergreen_startup(struct radeon_device *rdev) 
	if (r)

		return r;



	r = radeon_ib_pool_start(rdev);

	if (r)

		return r;



	r = radeon_ib_ring_tests(rdev);

	if (r)

	r = radeon_ib_pool_init(rdev);

	if (r) {

		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);

		return r;

	}



	r = r600_audio_init(rdev);

	if (r) {
@@ -3137,9 +3143,6 @@ int evergreen_suspend(struct radeon_device *rdev) 
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];



	r600_audio_fini(rdev);

	/* FIXME: we should wait for ring to be empty */

	radeon_ib_pool_suspend(rdev);

	r600_blit_suspend(rdev);

	r700_cp_stop(rdev);

	ring->ready = false;

	evergreen_irq_suspend(rdev);
@@ -3225,20 +3228,14 @@ int evergreen_init(struct radeon_device *rdev) 
	if (r)

		return r;



	r = radeon_ib_pool_init(rdev);

	rdev->accel_working = true;

	if (r) {

		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);

		rdev->accel_working = false;

	}



	r = evergreen_startup(rdev);

	if (r) {

		dev_err(rdev->dev, "disabling GPU acceleration\n");

		r700_cp_fini(rdev);

		r600_irq_fini(rdev);

		radeon_wb_fini(rdev);

		r100_ib_fini(rdev);

		radeon_ib_pool_fini(rdev);

		radeon_irq_kms_fini(rdev);

		evergreen_pcie_gart_fini(rdev);

		rdev->accel_working = false;
@@ -3265,7 +3262,7 @@ void evergreen_fini(struct radeon_device *rdev) 
	r700_cp_fini(rdev);

	r600_irq_fini(rdev);

	radeon_wb_fini(rdev);

	r100_ib_fini(rdev);

	radeon_ib_pool_fini(rdev);

	radeon_irq_kms_fini(rdev);

	evergreen_pcie_gart_fini(rdev);

	r600_vram_scratch_fini(rdev);

drivers/gpu/drm/radeon/evergreen_blit_kms.c

+20 −20
Original line number Diff line number Diff line
@@ -634,10 +634,6 @@ int evergreen_blit_init(struct radeon_device *rdev) 


	rdev->r600_blit.max_dim = 16384;



	/* pin copy shader into vram if already initialized */

	if (rdev->r600_blit.shader_obj)

		goto done;



	rdev->r600_blit.state_offset = 0;



	if (rdev->family < CHIP_CAYMAN)
@@ -668,13 +664,28 @@ int evergreen_blit_init(struct radeon_device *rdev) 
		obj_size += cayman_ps_size * 4;

	obj_size = ALIGN(obj_size, 256);



	r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,

	/* pin copy shader into vram if not already initialized */

	if (!rdev->r600_blit.shader_obj) {

		r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true,

				     RADEON_GEM_DOMAIN_VRAM,

				     NULL, &rdev->r600_blit.shader_obj);

		if (r) {

			DRM_ERROR("evergreen failed to allocate shader\n");

			return r;

		}



		r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);

		if (unlikely(r != 0))

			return r;

		r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,

				  &rdev->r600_blit.shader_gpu_addr);

		radeon_bo_unreserve(rdev->r600_blit.shader_obj);

		if (r) {

			dev_err(rdev->dev, "(%d) pin blit object failed\n", r);

			return r;

		}

	}



	DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",

		  obj_size,

		  rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
@@ -714,17 +725,6 @@ int evergreen_blit_init(struct radeon_device *rdev) 
	radeon_bo_kunmap(rdev->r600_blit.shader_obj);

	radeon_bo_unreserve(rdev->r600_blit.shader_obj);



done:

	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);

	if (unlikely(r != 0))

		return r;

	r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,

			  &rdev->r600_blit.shader_gpu_addr);

	radeon_bo_unreserve(rdev->r600_blit.shader_obj);

	if (r) {

		dev_err(rdev->dev, "(%d) pin blit object failed\n", r);

		return r;

	}

	radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);

	return 0;

}

drivers/gpu/drm/radeon/ni.c

+78 −102
Original line number Diff line number Diff line
@@ -855,6 +855,15 @@ void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 
	/* set to DX10/11 mode */

	radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));

	radeon_ring_write(ring, 1);



	if (ring->rptr_save_reg) {

		uint32_t next_rptr = ring->wptr + 3 + 4 + 8;

		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

		radeon_ring_write(ring, ((ring->rptr_save_reg - 

					  PACKET3_SET_CONFIG_REG_START) >> 2));

		radeon_ring_write(ring, next_rptr);

	}



	radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

	radeon_ring_write(ring,

#ifdef __BIG_ENDIAN
@@ -981,16 +990,41 @@ static int cayman_cp_start(struct radeon_device *rdev) 


static void cayman_cp_fini(struct radeon_device *rdev)

{

	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	cayman_cp_enable(rdev, false);

	radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);

	radeon_ring_fini(rdev, ring);

	radeon_scratch_free(rdev, ring->rptr_save_reg);

}



int cayman_cp_resume(struct radeon_device *rdev)

{

	static const int ridx[] = {

		RADEON_RING_TYPE_GFX_INDEX,

		CAYMAN_RING_TYPE_CP1_INDEX,

		CAYMAN_RING_TYPE_CP2_INDEX

	};

	static const unsigned cp_rb_cntl[] = {

		CP_RB0_CNTL,

		CP_RB1_CNTL,

		CP_RB2_CNTL,

	};

	static const unsigned cp_rb_rptr_addr[] = {

		CP_RB0_RPTR_ADDR,

		CP_RB1_RPTR_ADDR,

		CP_RB2_RPTR_ADDR

	};

	static const unsigned cp_rb_rptr_addr_hi[] = {

		CP_RB0_RPTR_ADDR_HI,

		CP_RB1_RPTR_ADDR_HI,

		CP_RB2_RPTR_ADDR_HI

	};

	static const unsigned cp_rb_base[] = {

		CP_RB0_BASE,

		CP_RB1_BASE,

		CP_RB2_BASE

	};

	struct radeon_ring *ring;

	u32 tmp;

	u32 rb_bufsz;

	int r;

	int i, r;



	/* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */

	WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
@@ -1012,91 +1046,47 @@ int cayman_cp_resume(struct radeon_device *rdev) 


	WREG32(CP_DEBUG, (1 << 27));



	/* ring 0 - compute and gfx */

	/* Set ring buffer size */

	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	rb_bufsz = drm_order(ring->ring_size / 8);

	tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;

#ifdef __BIG_ENDIAN

	tmp |= BUF_SWAP_32BIT;

#endif

	WREG32(CP_RB0_CNTL, tmp);



	/* Initialize the ring buffer's read and write pointers */

	WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);

	ring->wptr = 0;

	WREG32(CP_RB0_WPTR, ring->wptr);



	/* set the wb address wether it's enabled or not */

	WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);

	WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

	WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);



	if (rdev->wb.enabled)

	WREG32(SCRATCH_UMSK, 0xff);

	else {

		tmp |= RB_NO_UPDATE;

		WREG32(SCRATCH_UMSK, 0);

	}



	mdelay(1);

	WREG32(CP_RB0_CNTL, tmp);



	WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);



	ring->rptr = RREG32(CP_RB0_RPTR);

	for (i = 0; i < 3; ++i) {

		uint32_t rb_cntl;

		uint64_t addr;



	/* ring1  - compute only */

		/* Set ring buffer size */

	ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];

	rb_bufsz = drm_order(ring->ring_size / 8);

	tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;

		ring = &rdev->ring[ridx[i]];

		rb_cntl = drm_order(ring->ring_size / 8);

		rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8;

#ifdef __BIG_ENDIAN

	tmp |= BUF_SWAP_32BIT;

		rb_cntl |= BUF_SWAP_32BIT;

#endif

	WREG32(CP_RB1_CNTL, tmp);



	/* Initialize the ring buffer's read and write pointers */

	WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);

	ring->wptr = 0;

	WREG32(CP_RB1_WPTR, ring->wptr);

		WREG32(cp_rb_cntl[i], rb_cntl);



		/* set the wb address wether it's enabled or not */

	WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);

	WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);



	mdelay(1);

	WREG32(CP_RB1_CNTL, tmp);



	WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);



	ring->rptr = RREG32(CP_RB1_RPTR);

		addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;

		WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);

		WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);

	}



	/* ring2 - compute only */

	/* Set ring buffer size */

	ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];

	rb_bufsz = drm_order(ring->ring_size / 8);

	tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;

#ifdef __BIG_ENDIAN

	tmp |= BUF_SWAP_32BIT;

#endif

	WREG32(CP_RB2_CNTL, tmp);

	/* set the rb base addr, this causes an internal reset of ALL rings */

	for (i = 0; i < 3; ++i) {

		ring = &rdev->ring[ridx[i]];

		WREG32(cp_rb_base[i], ring->gpu_addr >> 8);

	}



	for (i = 0; i < 3; ++i) {

		/* Initialize the ring buffer's read and write pointers */

	WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);

	ring->wptr = 0;

	WREG32(CP_RB2_WPTR, ring->wptr);

		ring = &rdev->ring[ridx[i]];

		WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);



	/* set the wb address wether it's enabled or not */

	WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);

	WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);

		ring->rptr = ring->wptr = 0;

		WREG32(ring->rptr_reg, ring->rptr);

		WREG32(ring->wptr_reg, ring->wptr);



		mdelay(1);

	WREG32(CP_RB2_CNTL, tmp);



	WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);



	ring->rptr = RREG32(CP_RB2_RPTR);

		WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);

	}



	/* start the rings */

	cayman_cp_start(rdev);
@@ -1291,17 +1281,17 @@ static int cayman_startup(struct radeon_device *rdev) 
	if (r)

		return r;



	r = radeon_ib_pool_start(rdev);

	if (r)

		return r;



	r = radeon_ib_ring_tests(rdev);

	if (r)

	r = radeon_ib_pool_init(rdev);

	if (r) {

		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);

		return r;

	}



	r = radeon_vm_manager_start(rdev);

	if (r)

	r = radeon_vm_manager_init(rdev);

	if (r) {

		dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);

		return r;

	}



	r = r600_audio_init(rdev);

	if (r)
@@ -1334,10 +1324,6 @@ int cayman_resume(struct radeon_device *rdev) 
int cayman_suspend(struct radeon_device *rdev)

{

	r600_audio_fini(rdev);

	/* FIXME: we should wait for ring to be empty */

	radeon_ib_pool_suspend(rdev);

	radeon_vm_manager_suspend(rdev);

	r600_blit_suspend(rdev);

	cayman_cp_enable(rdev, false);

	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;

	evergreen_irq_suspend(rdev);
@@ -1413,17 +1399,7 @@ int cayman_init(struct radeon_device *rdev) 
	if (r)

		return r;



	r = radeon_ib_pool_init(rdev);

	rdev->accel_working = true;

	if (r) {

		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);

		rdev->accel_working = false;

	}

	r = radeon_vm_manager_init(rdev);

	if (r) {

		dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);

	}



	r = cayman_startup(rdev);

	if (r) {

		dev_err(rdev->dev, "disabling GPU acceleration\n");
@@ -1432,7 +1408,7 @@ int cayman_init(struct radeon_device *rdev) 
		if (rdev->flags & RADEON_IS_IGP)

			si_rlc_fini(rdev);

		radeon_wb_fini(rdev);

		r100_ib_fini(rdev);

		radeon_ib_pool_fini(rdev);

		radeon_vm_manager_fini(rdev);

		radeon_irq_kms_fini(rdev);

		cayman_pcie_gart_fini(rdev);
@@ -1463,7 +1439,7 @@ void cayman_fini(struct radeon_device *rdev) 
		si_rlc_fini(rdev);

	radeon_wb_fini(rdev);

	radeon_vm_manager_fini(rdev);

	r100_ib_fini(rdev);

	radeon_ib_pool_fini(rdev);

	radeon_irq_kms_fini(rdev);

	cayman_pcie_gart_fini(rdev);

	r600_vram_scratch_fini(rdev);

drivers/gpu/drm/radeon/r100.c

+6 −21
Original line number Diff line number Diff line
@@ -3722,12 +3722,6 @@ int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 
	return r;

}



void r100_ib_fini(struct radeon_device *rdev)

{

	radeon_ib_pool_suspend(rdev);

	radeon_ib_pool_fini(rdev);

}



void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)

{

	/* Shutdown CP we shouldn't need to do that but better be safe than
@@ -3887,13 +3881,11 @@ static int r100_startup(struct radeon_device *rdev) 
		return r;

	}



	r = radeon_ib_pool_start(rdev);

	if (r)

		return r;



	r = radeon_ib_ring_tests(rdev);

	if (r)

	r = radeon_ib_pool_init(rdev);

	if (r) {

		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);

		return r;

	}



	return 0;

}
@@ -3930,7 +3922,6 @@ int r100_resume(struct radeon_device *rdev) 


int r100_suspend(struct radeon_device *rdev)

{

	radeon_ib_pool_suspend(rdev);

	r100_cp_disable(rdev);

	radeon_wb_disable(rdev);

	r100_irq_disable(rdev);
@@ -3943,7 +3934,7 @@ void r100_fini(struct radeon_device *rdev) 
{

	r100_cp_fini(rdev);

	radeon_wb_fini(rdev);

	r100_ib_fini(rdev);

	radeon_ib_pool_fini(rdev);

	radeon_gem_fini(rdev);

	if (rdev->flags & RADEON_IS_PCI)

		r100_pci_gart_fini(rdev);
@@ -4050,20 +4041,14 @@ int r100_init(struct radeon_device *rdev) 
	}

	r100_set_safe_registers(rdev);



	r = radeon_ib_pool_init(rdev);

	rdev->accel_working = true;

	if (r) {

		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);

		rdev->accel_working = false;

	}



	r = r100_startup(rdev);

	if (r) {

		/* Somethings want wront with the accel init stop accel */

		dev_err(rdev->dev, "Disabling GPU acceleration\n");

		r100_cp_fini(rdev);

		radeon_wb_fini(rdev);

		r100_ib_fini(rdev);

		radeon_ib_pool_fini(rdev);

		radeon_irq_kms_fini(rdev);

		if (rdev->flags & RADEON_IS_PCI)

			r100_pci_gart_fini(rdev);

drivers/gpu/drm/radeon/r300.c

+6 −15
Original line number Diff line number Diff line
@@ -1391,13 +1391,11 @@ static int r300_startup(struct radeon_device *rdev) 
		return r;

	}



	r = radeon_ib_pool_start(rdev);

	if (r)

		return r;



	r = radeon_ib_ring_tests(rdev);

	if (r)

	r = radeon_ib_pool_init(rdev);

	if (r) {

		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);

		return r;

	}



	return 0;

}
@@ -1436,7 +1434,6 @@ int r300_resume(struct radeon_device *rdev) 


int r300_suspend(struct radeon_device *rdev)

{

	radeon_ib_pool_suspend(rdev);

	r100_cp_disable(rdev);

	radeon_wb_disable(rdev);

	r100_irq_disable(rdev);
@@ -1451,7 +1448,7 @@ void r300_fini(struct radeon_device *rdev) 
{

	r100_cp_fini(rdev);

	radeon_wb_fini(rdev);

	r100_ib_fini(rdev);

	radeon_ib_pool_fini(rdev);

	radeon_gem_fini(rdev);

	if (rdev->flags & RADEON_IS_PCIE)

		rv370_pcie_gart_fini(rdev);
@@ -1538,20 +1535,14 @@ int r300_init(struct radeon_device *rdev) 
	}

	r300_set_reg_safe(rdev);



	r = radeon_ib_pool_init(rdev);

	rdev->accel_working = true;

	if (r) {

		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);

		rdev->accel_working = false;

	}



	r = r300_startup(rdev);

	if (r) {

		/* Somethings want wront with the accel init stop accel */

		dev_err(rdev->dev, "Disabling GPU acceleration\n");

		r100_cp_fini(rdev);

		radeon_wb_fini(rdev);

		r100_ib_fini(rdev);

		radeon_ib_pool_fini(rdev);

		radeon_irq_kms_fini(rdev);

		if (rdev->flags & RADEON_IS_PCIE)

			rv370_pcie_gart_fini(rdev);