Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fa5fd7c6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 updates from Will Deacon:
 "Here is the core arm64 queue for 4.5.  As you might expect, the
  Christmas break resulted in a number of patches not making the final
  cut, so 4.6 is likely to be larger than usual.  There's still some
  useful stuff here, however, and it's detailed below.

  The EFI changes have been Reviewed-by Matt and the memblock change got
  an "OK" from akpm.

  Summary:

   - Support for a separate IRQ stack, although we haven't reduced the
     size of our thread stack just yet since we don't have enough data
     to determine a safe value

   - Refactoring of our EFI initialisation and runtime code into
     drivers/firmware/efi/ so that it can be reused by arch/arm/.

   - Ftrace improvements when unwinding in the function graph tracer

   - Document our silicon errata handling process

   - Cache flushing optimisation when mapping executable pages

   - Support for hugetlb mappings using the contiguous hint in the pte"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (45 commits)
  arm64: head.S: use memset to clear BSS
  efi: stub: define DISABLE_BRANCH_PROFILING for all architectures
  arm64: entry: remove pointless SPSR mode check
  arm64: mm: move pgd_cache initialisation to pgtable_cache_init
  arm64: module: avoid undefined shift behavior in reloc_data()
  arm64: module: fix relocation of movz instruction with negative immediate
  arm64: traps: address fallout from printk -> pr_* conversion
  arm64: ftrace: fix a stack tracer's output under function graph tracer
  arm64: pass a task parameter to unwind_frame()
  arm64: ftrace: modify a stack frame in a safe way
  arm64: remove irq_count and do_softirq_own_stack()
  arm64: hugetlb: add support for PTE contiguous bit
  arm64: Use PoU cache instr for I/D coherency
  arm64: Defer dcache flush in __cpu_copy_user_page
  arm64: reduce stack use in irq_handler
  arm64: mm: ensure that the zero page is visible to the page table walker
  arm64: Documentation: add list of software workarounds for errata
  arm64: mm: place __cpu_setup in .text
  arm64: cmpxchg: Don't incldue linux/mmdebug.h
  arm64: mm: fold alternatives into .init
  ...
parents 19e2fc40 2a803c4d

Documentation/arm64/silicon-errata.txt

0 → 100644
+58 −0
Original line number Diff line number Diff line 
                Silicon Errata and Software Workarounds

                =======================================



Author: Will Deacon <will.deacon@arm.com>

Date  : 27 November 2015



It is an unfortunate fact of life that hardware is often produced with

so-called "errata", which can cause it to deviate from the architecture

under specific circumstances.  For hardware produced by ARM, these

errata are broadly classified into the following categories:



  Category A: A critical error without a viable workaround.

  Category B: A significant or critical error with an acceptable

              workaround.

  Category C: A minor error that is not expected to occur under normal

              operation.



For more information, consult one of the "Software Developers Errata

Notice" documents available on infocenter.arm.com (registration

required).



As far as Linux is concerned, Category B errata may require some special

treatment in the operating system. For example, avoiding a particular

sequence of code, or configuring the processor in a particular way. A

less common situation may require similar actions in order to declassify

a Category A erratum into a Category C erratum. These are collectively

known as "software workarounds" and are only required in the minority of

cases (e.g. those cases that both require a non-secure workaround *and*

can be triggered by Linux).



For software workarounds that may adversely impact systems unaffected by

the erratum in question, a Kconfig entry is added under "Kernel

Features" -> "ARM errata workarounds via the alternatives framework".

These are enabled by default and patched in at runtime when an affected

CPU is detected. For less-intrusive workarounds, a Kconfig option is not

available and the code is structured (preferably with a comment) in such

a way that the erratum will not be hit.



This approach can make it slightly onerous to determine exactly which

errata are worked around in an arbitrary kernel source tree, so this

file acts as a registry of software workarounds in the Linux Kernel and

will be updated when new workarounds are committed and backported to

stable kernels.



| Implementor    | Component       | Erratum ID      | Kconfig                 |

+----------------+-----------------+-----------------+-------------------------+

| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319    |

| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319    |

| ARM            | Cortex-A53      | #824069         | ARM64_ERRATUM_824069    |

| ARM            | Cortex-A53      | #819472         | ARM64_ERRATUM_819472    |

| ARM            | Cortex-A53      | #845719         | ARM64_ERRATUM_845719    |

| ARM            | Cortex-A53      | #843419         | ARM64_ERRATUM_843419    |

| ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075    |

| ARM            | Cortex-A57      | #852523         | N/A                     |

| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220    |

|                |                 |                 |                         |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375    |

| Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |

Documentation/features/time/irq-time-acct/arch-support.txt

+1 −1
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ 
    |       alpha: |  ..  |

    |         arc: | TODO |

    |         arm: |  ok  |

    |       arm64: |  ..  |

    |       arm64: |  ok  |

    |       avr32: | TODO |

    |    blackfin: | TODO |

    |         c6x: | TODO |

arch/arm64/Kconfig

+1 −3
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ config ARM64 
	select HAVE_FUNCTION_GRAPH_TRACER

	select HAVE_GENERIC_DMA_COHERENT

	select HAVE_HW_BREAKPOINT if PERF_EVENTS

	select HAVE_IRQ_TIME_ACCOUNTING

	select HAVE_MEMBLOCK

	select HAVE_PATA_PLATFORM

	select HAVE_PERF_EVENTS
@@ -529,9 +530,6 @@ config HW_PERF_EVENTS 
config SYS_SUPPORTS_HUGETLBFS

	def_bool y



config ARCH_WANT_GENERAL_HUGETLB

	def_bool y



config ARCH_WANT_HUGE_PMD_SHARE

	def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)

arch/arm64/include/asm/alternative.h

+0 −1
Original line number Diff line number Diff line
@@ -19,7 +19,6 @@ struct alt_instr { 


void __init apply_alternatives_all(void);

void apply_alternatives(void *start, size_t length);

void free_alternatives_memory(void);



#define ALTINSTR_ENTRY(feature)						      \

	" .word 661b - .\n"				/* label           */ \

arch/arm64/include/asm/assembler.h

+11 −0
Original line number Diff line number Diff line
@@ -193,6 +193,17 @@ lr .req x30 // link register 
	str	\src, [\tmp, :lo12:\sym]

	.endm



	/*

	 * @sym: The name of the per-cpu variable

	 * @reg: Result of per_cpu(sym, smp_processor_id())

	 * @tmp: scratch register

	 */

	.macro this_cpu_ptr, sym, reg, tmp

	adr_l	\reg, \sym

	mrs	\tmp, tpidr_el1

	add	\reg, \reg, \tmp

	.endm



/*

 * Annotate a function as position independent, i.e., safe to be called before

 * the kernel virtual mapping is activated.