[ARM] Separate VIC (vectored interrupt controller) support from Versatile (fa0fe48f) · Commits · e / devices / android_kernel_teracube_2e

arch/arm/Kconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -180,6 +180,7 @@ config ARCH_OMAP
		config ARCH_VERSATILE
		bool "Versatile"
		select ARM_AMBA
		select ARM_VIC
		select ICST307
		help
		This enables support for ARM Ltd Versatile board.

arch/arm/common/Kconfig

+5 −2

Original line number	Diff line number	Diff line
		config ICST525
		config ARM_GIC
		bool

		config ARM_GIC
		config ARM_VIC
		bool

		config ICST525
		bool

		config ICST307

arch/arm/common/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -4,6 +4,7 @@

		obj-y += rtctime.o
		obj-$(CONFIG_ARM_GIC) += gic.o
		obj-$(CONFIG_ARM_VIC) += vic.o
		obj-$(CONFIG_ICST525) += icst525.o
		obj-$(CONFIG_ICST307) += icst307.o
		obj-$(CONFIG_SA1111) += sa1111.o

arch/arm/common/vic.c

0 → 100644

+92 −0

Original line number	Diff line number	Diff line
		/*
		* linux/arch/arm/common/vic.c
		*
		* Copyright (C) 1999 - 2003 ARM Limited
		* Copyright (C) 2000 Deep Blue Solutions Ltd
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		* the Free Software Foundation; either version 2 of the License, or
		* (at your option) any later version.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		* You should have received a copy of the GNU General Public License
		* along with this program; if not, write to the Free Software
		* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		*/
		#include <linux/init.h>
		#include <linux/list.h>

		#include <asm/io.h>
		#include <asm/irq.h>
		#include <asm/mach/irq.h>
		#include <asm/hardware/vic.h>

		static void __iomem *vic_base;

		static void vic_mask_irq(unsigned int irq)
		{
		irq -= IRQ_VIC_START;
		writel(1 << irq, vic_base + VIC_INT_ENABLE_CLEAR);
		}

		static void vic_unmask_irq(unsigned int irq)
		{
		irq -= IRQ_VIC_START;
		writel(1 << irq, vic_base + VIC_INT_ENABLE);
		}

		static struct irqchip vic_chip = {
		.ack = vic_mask_irq,
		.mask = vic_mask_irq,
		.unmask = vic_unmask_irq,
		};

		void __init vic_init(void __iomem *base, u32 vic_sources)
		{
		unsigned int i;

		vic_base = base;

		/* Disable all interrupts initially. */

		writel(0, vic_base + VIC_INT_SELECT);
		writel(0, vic_base + VIC_INT_ENABLE);
		writel(~0, vic_base + VIC_INT_ENABLE_CLEAR);
		writel(0, vic_base + VIC_IRQ_STATUS);
		writel(0, vic_base + VIC_ITCR);
		writel(~0, vic_base + VIC_INT_SOFT_CLEAR);

		/*
		* Make sure we clear all existing interrupts
		*/
		writel(0, vic_base + VIC_VECT_ADDR);
		for (i = 0; i < 19; i++) {
		unsigned int value;

		value = readl(vic_base + VIC_VECT_ADDR);
		writel(value, vic_base + VIC_VECT_ADDR);
		}

		for (i = 0; i < 16; i++) {
		void __iomem reg = vic_base + VIC_VECT_CNTL0 + (i 4);
		writel(VIC_VECT_CNTL_ENABLE \| i, reg);
		}

		writel(32, vic_base + VIC_DEF_VECT_ADDR);

		for (i = 0; i < 32; i++) {
		unsigned int irq = IRQ_VIC_START + i;

		set_irq_chip(irq, &vic_chip);

		if (vic_sources & (1 << i)) {
		set_irq_handler(irq, do_level_IRQ);
		set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
		}
		}
		}

arch/arm/mach-versatile/core.c

+5 −53

Original line number	Diff line number	Diff line
		@@ -35,6 +35,7 @@
		#include <asm/leds.h>
		#include <asm/hardware/arm_timer.h>
		#include <asm/hardware/icst307.h>
		#include <asm/hardware/vic.h>

		#include <asm/mach/arch.h>
		#include <asm/mach/flash.h>
		@@ -56,24 +57,6 @@
		#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
		#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)

		static void vic_mask_irq(unsigned int irq)
		{
		irq -= IRQ_VIC_START;
		writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
		}

		static void vic_unmask_irq(unsigned int irq)
		{
		irq -= IRQ_VIC_START;
		writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE);
		}

		static struct irqchip vic_chip = {
		.ack = vic_mask_irq,
		.mask = vic_mask_irq,
		.unmask = vic_unmask_irq,
		};

		static void sic_mask_irq(unsigned int irq)
		{
		irq -= IRQ_SIC_START;
		@@ -127,43 +110,12 @@ sic_handle_irq(unsigned int irq, struct irqdesc desc, struct pt_regs regs)

		void __init versatile_init_irq(void)
		{
		unsigned int i, value;

		/* Disable all interrupts initially. */
		unsigned int i;

		writel(0, VA_VIC_BASE + VIC_INT_SELECT);
		writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
		writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
		writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
		writel(0, VA_VIC_BASE + VIC_ITCR);
		writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);

		/*
		* Make sure we clear all existing interrupts
		*/
		writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
		for (i = 0; i < 19; i++) {
		value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
		writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
		}

		for (i = 0; i < 16; i++) {
		value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
		writel(value \| VICVectCntl_Enable \| i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
		}

		writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);

		for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
		if (i != IRQ_VICSOURCE31) {
		set_irq_chip(i, &vic_chip);
		set_irq_handler(i, do_level_IRQ);
		set_irq_flags(i, IRQF_VALID \| IRQF_PROBE);
		}
		}
		vic_init(VA_VIC_BASE, ~(1 << 31));

		set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
		vic_unmask_irq(IRQ_VICSOURCE31);
		enable_irq(IRQ_VICSOURCE31);

		/* Do second interrupt controller */
		writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
		@@ -877,7 +829,7 @@ static unsigned long versatile_gettimeoffset(void)
		ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
		do {
		ticks1 = ticks2;
		status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
		status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS);
		ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
		} while (ticks2 > ticks1);