Merge remote-tracking branches 'spi/topic/atmel', 'spi/topic/bcm2385',... (f9de7342) · Commits · e / devices / android_kernel_teracube_2e

drivers/spi/spi-atmel.c

+7 −1

Original line number	Diff line number	Diff line
		@@ -180,11 +180,17 @@
		\| SPI_BF(name, value))

		/* Register access macros */
		#ifdef CONFIG_AVR32
		#define spi_readl(port, reg) \
		__raw_readl((port)->regs + SPI_##reg)
		#define spi_writel(port, reg, value) \
		__raw_writel((value), (port)->regs + SPI_##reg)

		#else
		#define spi_readl(port, reg) \
		readl_relaxed((port)->regs + SPI_##reg)
		#define spi_writel(port, reg, value) \
		writel_relaxed((value), (port)->regs + SPI_##reg)
		#endif
		/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
		* cache operations; better heuristics consider wordsize and bitrate.
		*/

drivers/spi/spi-bcm2835.c

+253 −138

Original line number	Diff line number	Diff line
		@@ -3,6 +3,7 @@
		*
		* Copyright (C) 2012 Chris Boot
		* Copyright (C) 2013 Stephen Warren
		* Copyright (C) 2015 Martin Sperl
		*
		* This driver is inspired by:
		* spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
		@@ -29,6 +30,7 @@
		#include <linux/module.h>
		#include <linux/of.h>
		#include <linux/of_irq.h>
		#include <linux/of_gpio.h>
		#include <linux/of_device.h>
		#include <linux/spi/spi.h>

		@@ -66,8 +68,10 @@
		#define BCM2835_SPI_CS_CS_10 0x00000002
		#define BCM2835_SPI_CS_CS_01 0x00000001

		#define BCM2835_SPI_POLLING_LIMIT_US 30
		#define BCM2835_SPI_TIMEOUT_MS 30000
		#define BCM2835_SPI_MODE_BITS (SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \| SPI_NO_CS)
		#define BCM2835_SPI_MODE_BITS (SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \
		\| SPI_NO_CS \| SPI_3WIRE)

		#define DRV_NAME "spi-bcm2835"

		@@ -75,10 +79,10 @@ struct bcm2835_spi {
		void __iomem *regs;
		struct clk *clk;
		int irq;
		struct completion done;
		const u8 *tx_buf;
		u8 *rx_buf;
		int len;
		int tx_len;
		int rx_len;
		};

		static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
		@@ -91,205 +95,315 @@ static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
		writel(val, bs->regs + reg);
		}

		static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs, int len)
		static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
		{
		u8 byte;

		while (len--) {
		while ((bs->rx_len) &&
		(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
		byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
		if (bs->rx_buf)
		*bs->rx_buf++ = byte;
		bs->rx_len--;
		}
		}

		static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs, int len)
		static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
		{
		u8 byte;

		if (len > bs->len)
		len = bs->len;

		while (len--) {
		while ((bs->tx_len) &&
		(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
		byte = bs->tx_buf ? *bs->tx_buf++ : 0;
		bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
		bs->len--;
		bs->tx_len--;
		}
		}

		static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
		static void bcm2835_spi_reset_hw(struct spi_master *master)
		{
		struct spi_master *master = dev_id;
		struct bcm2835_spi *bs = spi_master_get_devdata(master);
		u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);

		/*
		* RXR - RX needs Reading. This means 12 (or more) bytes have been
		* transmitted and hence 12 (or more) bytes have been received.
		*
		* The FIFO is 16-bytes deep. We check for this interrupt to keep the
		* FIFO full; we have a 4-byte-time buffer for IRQ latency. We check
		* this before DONE (TX empty) just in case we delayed processing this
		* interrupt for some reason.
		*
		* We only check for this case if we have more bytes to TX; at the end
		* of the transfer, we ignore this pipelining optimization, and let
		* bcm2835_spi_finish_transfer() drain the RX FIFO.
		*/
		if (bs->len && (cs & BCM2835_SPI_CS_RXR)) {
		/* Read 12 bytes of data */
		bcm2835_rd_fifo(bs, 12);
		/* Disable SPI interrupts and transfer */
		cs &= ~(BCM2835_SPI_CS_INTR \|
		BCM2835_SPI_CS_INTD \|
		BCM2835_SPI_CS_TA);
		/* and reset RX/TX FIFOS */
		cs \|= BCM2835_SPI_CS_CLEAR_RX \| BCM2835_SPI_CS_CLEAR_TX;

		/* Write up to 12 bytes */
		bcm2835_wr_fifo(bs, 12);
		/* and reset the SPI_HW */
		bcm2835_wr(bs, BCM2835_SPI_CS, cs);
		}

		static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
		{
		struct spi_master *master = dev_id;
		struct bcm2835_spi *bs = spi_master_get_devdata(master);

		/* Read as many bytes as possible from FIFO */
		bcm2835_rd_fifo(bs);
		/* Write as many bytes as possible to FIFO */
		bcm2835_wr_fifo(bs);

		/* based on flags decide if we can finish the transfer */
		if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) {
		/* Transfer complete - reset SPI HW */
		bcm2835_spi_reset_hw(master);
		/* wake up the framework */
		complete(&master->xfer_completion);
		}

		/*
		* We must have written something to the TX FIFO due to the
		* bs->len check above, so cannot be DONE. Hence, return
		* early. Note that DONE could also be set if we serviced an
		* RXR interrupt really late.
		*/
		return IRQ_HANDLED;
		}

		/*
		* DONE - TX empty. This occurs when we first enable the transfer
		* since we do not pre-fill the TX FIFO. At any other time, given that
		* we refill the TX FIFO above based on RXR, and hence ignore DONE if
		* RXR is set, DONE really does mean end-of-transfer.
		static int bcm2835_spi_transfer_one_poll(struct spi_master *master,
		struct spi_device *spi,
		struct spi_transfer *tfr,
		u32 cs,
		unsigned long xfer_time_us)
		{
		struct bcm2835_spi *bs = spi_master_get_devdata(master);
		unsigned long timeout = jiffies +
		max(4 * xfer_time_us * HZ / 1000000, 2uL);

		/* enable HW block without interrupts */
		bcm2835_wr(bs, BCM2835_SPI_CS, cs \| BCM2835_SPI_CS_TA);

		/* set timeout to 4x the expected time, or 2 jiffies */
		/* loop until finished the transfer */
		while (bs->rx_len) {
		/* read from fifo as much as possible */
		bcm2835_rd_fifo(bs);
		/* fill in tx fifo as much as possible */
		bcm2835_wr_fifo(bs);
		/* if we still expect some data after the read,
		* check for a possible timeout
		*/
		if (cs & BCM2835_SPI_CS_DONE) {
		if (bs->len) { /* First interrupt in a transfer */
		bcm2835_wr_fifo(bs, 16);
		} else { /* Transfer complete */
		/* Disable SPI interrupts */
		cs &= ~(BCM2835_SPI_CS_INTR \| BCM2835_SPI_CS_INTD);
		bcm2835_wr(bs, BCM2835_SPI_CS, cs);
		if (bs->rx_len && time_after(jiffies, timeout)) {
		/* Transfer complete - reset SPI HW */
		bcm2835_spi_reset_hw(master);
		/* and return timeout */
		return -ETIMEDOUT;
		}
		}

		/*
		* Wake up bcm2835_spi_transfer_one(), which will call
		* bcm2835_spi_finish_transfer(), to drain the RX FIFO.
		*/
		complete(&bs->done);
		/* Transfer complete - reset SPI HW */
		bcm2835_spi_reset_hw(master);
		/* and return without waiting for completion */
		return 0;
		}

		return IRQ_HANDLED;
		static int bcm2835_spi_transfer_one_irq(struct spi_master *master,
		struct spi_device *spi,
		struct spi_transfer *tfr,
		u32 cs)
		{
		struct bcm2835_spi *bs = spi_master_get_devdata(master);

		/* fill in fifo if we have gpio-cs
		* note that there have been rare events where the native-CS
		* flapped for <1us which may change the behaviour
		* with gpio-cs this does not happen, so it is implemented
		* only for this case
		*/
		if (gpio_is_valid(spi->cs_gpio)) {
		/* enable HW block, but without interrupts enabled
		* this would triggern an immediate interrupt
		*/
		bcm2835_wr(bs, BCM2835_SPI_CS,
		cs \| BCM2835_SPI_CS_TA);
		/* fill in tx fifo as much as possible */
		bcm2835_wr_fifo(bs);
		}

		return IRQ_NONE;
		/*
		* Enable the HW block. This will immediately trigger a DONE (TX
		* empty) interrupt, upon which we will fill the TX FIFO with the
		* first TX bytes. Pre-filling the TX FIFO here to avoid the
		* interrupt doesn't work:-(
		*/
		cs \|= BCM2835_SPI_CS_INTR \| BCM2835_SPI_CS_INTD \| BCM2835_SPI_CS_TA;
		bcm2835_wr(bs, BCM2835_SPI_CS, cs);

		/* signal that we need to wait for completion */
		return 1;
		}

		static int bcm2835_spi_start_transfer(struct spi_device *spi,
		static int bcm2835_spi_transfer_one(struct spi_master *master,
		struct spi_device *spi,
		struct spi_transfer *tfr)
		{
		struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
		struct bcm2835_spi *bs = spi_master_get_devdata(master);
		unsigned long spi_hz, clk_hz, cdiv;
		u32 cs = BCM2835_SPI_CS_INTR \| BCM2835_SPI_CS_INTD \| BCM2835_SPI_CS_TA;
		unsigned long spi_used_hz, xfer_time_us;
		u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);

		/* set clock */
		spi_hz = tfr->speed_hz;
		clk_hz = clk_get_rate(bs->clk);

		if (spi_hz >= clk_hz / 2) {
		cdiv = 2; /* clk_hz/2 is the fastest we can go */
		} else if (spi_hz) {
		/* CDIV must be a power of two */
		cdiv = roundup_pow_of_two(DIV_ROUND_UP(clk_hz, spi_hz));
		/* CDIV must be a multiple of two */
		cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
		cdiv += (cdiv % 2);

		if (cdiv >= 65536)
		cdiv = 0; /* 0 is the slowest we can go */
		} else
		} else {
		cdiv = 0; /* 0 is the slowest we can go */
		}
		spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
		bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);

		/* handle all the modes */
		if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
		cs \|= BCM2835_SPI_CS_REN;
		if (spi->mode & SPI_CPOL)
		cs \|= BCM2835_SPI_CS_CPOL;
		if (spi->mode & SPI_CPHA)
		cs \|= BCM2835_SPI_CS_CPHA;

		if (!(spi->mode & SPI_NO_CS)) {
		if (spi->mode & SPI_CS_HIGH) {
		cs \|= BCM2835_SPI_CS_CSPOL;
		cs \|= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
		}

		cs \|= spi->chip_select;
		}
		/* for gpio_cs set dummy CS so that no HW-CS get changed
		* we can not run this in bcm2835_spi_set_cs, as it does
		* not get called for cs_gpio cases, so we need to do it here
		*/
		if (gpio_is_valid(spi->cs_gpio) \|\| (spi->mode & SPI_NO_CS))
		cs \|= BCM2835_SPI_CS_CS_10 \| BCM2835_SPI_CS_CS_01;

		reinit_completion(&bs->done);
		/* set transmit buffers and length */
		bs->tx_buf = tfr->tx_buf;
		bs->rx_buf = tfr->rx_buf;
		bs->len = tfr->len;
		bs->tx_len = tfr->len;
		bs->rx_len = tfr->len;

		bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
		/*
		* Enable the HW block. This will immediately trigger a DONE (TX
		* empty) interrupt, upon which we will fill the TX FIFO with the
		* first TX bytes. Pre-filling the TX FIFO here to avoid the
		* interrupt doesn't work:-(
		*/
		bcm2835_wr(bs, BCM2835_SPI_CS, cs);
		/* calculate the estimated time in us the transfer runs */
		xfer_time_us = tfr->len
		* 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */
		* 1000000 / spi_used_hz;

		return 0;
		/* for short requests run polling*/
		if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US)
		return bcm2835_spi_transfer_one_poll(master, spi, tfr,
		cs, xfer_time_us);

		return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs);
		}

		static int bcm2835_spi_finish_transfer(struct spi_device *spi,
		struct spi_transfer *tfr, bool cs_change)
		static void bcm2835_spi_handle_err(struct spi_master *master,
		struct spi_message *msg)
		{
		struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
		bcm2835_spi_reset_hw(master);
		}

		static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level)
		{
		/*
		* we can assume that we are "native" as per spi_set_cs
		* calling us ONLY when cs_gpio is not set
		* we can also assume that we are CS < 3 as per bcm2835_spi_setup
		* we would not get called because of error handling there.
		* the level passed is the electrical level not enabled/disabled
		* so it has to get translated back to enable/disable
		* see spi_set_cs in spi.c for the implementation
		*/

		struct spi_master *master = spi->master;
		struct bcm2835_spi *bs = spi_master_get_devdata(master);
		u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
		bool enable;

		/* Drain RX FIFO */
		while (cs & BCM2835_SPI_CS_RXD) {
		bcm2835_rd_fifo(bs, 1);
		cs = bcm2835_rd(bs, BCM2835_SPI_CS);
		}
		/* calculate the enable flag from the passed gpio_level */
		enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level;

		if (tfr->delay_usecs)
		udelay(tfr->delay_usecs);
		/* set flags for "reverse" polarity in the registers */
		if (spi->mode & SPI_CS_HIGH) {
		/* set the correct CS-bits */
		cs \|= BCM2835_SPI_CS_CSPOL;
		cs \|= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
		} else {
		/* clean the CS-bits */
		cs &= ~BCM2835_SPI_CS_CSPOL;
		cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select);
		}

		if (cs_change)
		/* Clear TA flag */
		bcm2835_wr(bs, BCM2835_SPI_CS, cs & ~BCM2835_SPI_CS_TA);
		/* select the correct chip_select depending on disabled/enabled */
		if (enable) {
		/* set cs correctly */
		if (spi->mode & SPI_NO_CS) {
		/* use the "undefined" chip-select */
		cs \|= BCM2835_SPI_CS_CS_10 \| BCM2835_SPI_CS_CS_01;
		} else {
		/* set the chip select */
		cs &= ~(BCM2835_SPI_CS_CS_10 \| BCM2835_SPI_CS_CS_01);
		cs \|= spi->chip_select;
		}
		} else {
		/* disable CSPOL which puts HW-CS into deselected state */
		cs &= ~BCM2835_SPI_CS_CSPOL;
		/* use the "undefined" chip-select as precaution */
		cs \|= BCM2835_SPI_CS_CS_10 \| BCM2835_SPI_CS_CS_01;
		}

		return 0;
		/* finally set the calculated flags in SPI_CS */
		bcm2835_wr(bs, BCM2835_SPI_CS, cs);
		}

		static int bcm2835_spi_transfer_one(struct spi_master *master,
		struct spi_message *mesg)
		static int chip_match_name(struct gpio_chip chip, void data)
		{
		struct bcm2835_spi *bs = spi_master_get_devdata(master);
		struct spi_transfer *tfr;
		struct spi_device *spi = mesg->spi;
		int err = 0;
		unsigned int timeout;
		bool cs_change;

		list_for_each_entry(tfr, &mesg->transfers, transfer_list) {
		err = bcm2835_spi_start_transfer(spi, tfr);
		if (err)
		goto out;
		return !strcmp(chip->label, data);
		}

		timeout = wait_for_completion_timeout(&bs->done,
		msecs_to_jiffies(BCM2835_SPI_TIMEOUT_MS));
		if (!timeout) {
		err = -ETIMEDOUT;
		goto out;
		static int bcm2835_spi_setup(struct spi_device *spi)
		{
		int err;
		struct gpio_chip *chip;
		/*
		* sanity checking the native-chipselects
		*/
		if (spi->mode & SPI_NO_CS)
		return 0;
		if (gpio_is_valid(spi->cs_gpio))
		return 0;
		if (spi->chip_select > 1) {
		/* error in the case of native CS requested with CS > 1
		* officially there is a CS2, but it is not documented
		* which GPIO is connected with that...
		*/
		dev_err(&spi->dev,
		"setup: only two native chip-selects are supported\n");
		return -EINVAL;
		}
		/* now translate native cs to GPIO */

		cs_change = tfr->cs_change \|\|
		list_is_last(&tfr->transfer_list, &mesg->transfers);
		/* get the gpio chip for the base */
		chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
		if (!chip)
		return 0;

		err = bcm2835_spi_finish_transfer(spi, tfr, cs_change);
		if (err)
		goto out;
		/* and calculate the real CS */
		spi->cs_gpio = chip->base + 8 - spi->chip_select;

		mesg->actual_length += (tfr->len - bs->len);
		}
		/* and set up the "mode" and level */
		dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
		spi->chip_select, spi->cs_gpio);

		out:
		/* Clear FIFOs, and disable the HW block */
		bcm2835_wr(bs, BCM2835_SPI_CS,
		BCM2835_SPI_CS_CLEAR_RX \| BCM2835_SPI_CS_CLEAR_TX);
		mesg->status = err;
		spi_finalize_current_message(master);
		/* set up GPIO as output and pull to the correct level */
		err = gpio_direction_output(spi->cs_gpio,
		(spi->mode & SPI_CS_HIGH) ? 0 : 1);
		if (err) {
		dev_err(&spi->dev,
		"could not set CS%i gpio %i as output: %i",
		spi->chip_select, spi->cs_gpio, err);
		return err;
		}
		/* the implementation of pinctrl-bcm2835 currently does not
		* set the GPIO value when using gpio_direction_output
		* so we are setting it here explicitly
		*/
		gpio_set_value(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ? 0 : 1);

		return 0;
		}
		@@ -312,13 +426,14 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
		master->mode_bits = BCM2835_SPI_MODE_BITS;
		master->bits_per_word_mask = SPI_BPW_MASK(8);
		master->num_chipselect = 3;
		master->transfer_one_message = bcm2835_spi_transfer_one;
		master->setup = bcm2835_spi_setup;
		master->set_cs = bcm2835_spi_set_cs;
		master->transfer_one = bcm2835_spi_transfer_one;
		master->handle_err = bcm2835_spi_handle_err;
		master->dev.of_node = pdev->dev.of_node;

		bs = spi_master_get_devdata(master);

		init_completion(&bs->done);

		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		bs->regs = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(bs->regs)) {
		@@ -349,7 +464,7 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
		goto out_clk_disable;
		}

		/* initialise the hardware */
		/* initialise the hardware with the default polarities */
		bcm2835_wr(bs, BCM2835_SPI_CS,
		BCM2835_SPI_CS_CLEAR_RX \| BCM2835_SPI_CS_CLEAR_TX);

drivers/spi/spi-bcm53xx.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -44,7 +44,7 @@ static int bcm53xxspi_wait(struct bcm53xxspi *b53spi, unsigned int timeout_ms)
		u32 tmp;

		/* SPE bit has to be 0 before we read MSPI STATUS */
		deadline = jiffies + BCM53XXSPI_SPE_TIMEOUT_MS * HZ / 1000;
		deadline = jiffies + msecs_to_jiffies(BCM53XXSPI_SPE_TIMEOUT_MS);
		do {
		tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
		if (!(tmp & B53SPI_MSPI_SPCR2_SPE))
		@@ -56,7 +56,7 @@ static int bcm53xxspi_wait(struct bcm53xxspi *b53spi, unsigned int timeout_ms)
		goto spi_timeout;

		/* Check status */
		deadline = jiffies + timeout_ms * HZ / 1000;
		deadline = jiffies + msecs_to_jiffies(timeout_ms);
		do {
		tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_MSPI_STATUS);
		if (tmp & B53SPI_MSPI_MSPI_STATUS_SPIF) {

drivers/spi/spi-bitbang-txrx.h

+14 −4

Original line number	Diff line number	Diff line
		@@ -49,12 +49,17 @@ bitbang_txrx_be_cpha0(struct spi_device *spi,
		{
		/* if (cpol == 0) this is SPI_MODE_0; else this is SPI_MODE_2 */

		bool oldbit = !(word & 1);
		/* clock starts at inactive polarity */
		for (word <<= (32 - bits); likely(bits); bits--) {

		/* setup MSB (to slave) on trailing edge */
		if ((flags & SPI_MASTER_NO_TX) == 0)
		if ((flags & SPI_MASTER_NO_TX) == 0) {
		if ((word & (1 << 31)) != oldbit) {
		setmosi(spi, word & (1 << 31));
		oldbit = word & (1 << 31);
		}
		}
		spidelay(nsecs); /* T(setup) */

		setsck(spi, !cpol);
		@@ -76,13 +81,18 @@ bitbang_txrx_be_cpha1(struct spi_device *spi,
		{
		/* if (cpol == 0) this is SPI_MODE_1; else this is SPI_MODE_3 */

		bool oldbit = !(word & (1 << 31));
		/* clock starts at inactive polarity */
		for (word <<= (32 - bits); likely(bits); bits--) {

		/* setup MSB (to slave) on leading edge */
		setsck(spi, !cpol);
		if ((flags & SPI_MASTER_NO_TX) == 0)
		if ((flags & SPI_MASTER_NO_TX) == 0) {
		if ((word & (1 << 31)) != oldbit) {
		setmosi(spi, word & (1 << 31));
		oldbit = word & (1 << 31);
		}
		}
		spidelay(nsecs); /* T(setup) */

		setsck(spi, cpol);

drivers/spi/spi.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -850,6 +850,9 @@ static int spi_transfer_one_message(struct spi_master *master,
		if (msg->status == -EINPROGRESS)
		msg->status = ret;

		if (msg->status)
		master->handle_err(master, msg);

		spi_finalize_current_message(master);

		return ret;