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Commit f9a4ea35 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Fix serialisation of pipecontrol write vs semaphore signal 



In order for the MI_SEMAPHORE_SIGNAL command to wait until after the
pipecontrol writing the signal value is complete, we have to pause the
CS inside the PIPE_CONTROL with the CS_STALL bit.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461932305-14637-4-git-send-email-chris@chris-wilson.co.uk
parent 215a7e32

drivers/gpu/drm/i915/intel_ringbuffer.c

+1 −2
Original line number Diff line number Diff line
@@ -1307,7 +1307,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, 
		intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));

		intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |

					   PIPE_CONTROL_QW_WRITE |

					   PIPE_CONTROL_FLUSH_ENABLE);

					   PIPE_CONTROL_CS_STALL);

		intel_ring_emit(signaller, lower_32_bits(gtt_offset));

		intel_ring_emit(signaller, upper_32_bits(gtt_offset));

		intel_ring_emit(signaller, seqno);
@@ -1489,7 +1489,6 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req, 


	intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |

				MI_SEMAPHORE_GLOBAL_GTT |

				MI_SEMAPHORE_POLL |

				MI_SEMAPHORE_SAD_GTE_SDD);

	intel_ring_emit(waiter, seqno);

	intel_ring_emit(waiter,