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Commit f992c241 authored by Laurent Pinchart's avatar Laurent Pinchart
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clocksource: sh_mtu2: Replace hardcoded register values with macros 



Define symbolic macros for all used registers bits.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: default avatarWolfram Sang <wsa@sang-engineering.com>
parent c54ccb43

drivers/clocksource/sh_mtu2.c

+92 −6
Original line number Diff line number Diff line
@@ -67,6 +67,88 @@ static DEFINE_RAW_SPINLOCK(sh_mtu2_lock); 
#define TCNT 5 /* channel register */

#define TGR  6 /* channel register */



#define TCR_CCLR_NONE		(0 << 5)

#define TCR_CCLR_TGRA		(1 << 5)

#define TCR_CCLR_TGRB		(2 << 5)

#define TCR_CCLR_SYNC		(3 << 5)

#define TCR_CCLR_TGRC		(5 << 5)

#define TCR_CCLR_TGRD		(6 << 5)

#define TCR_CCLR_MASK		(7 << 5)

#define TCR_CKEG_RISING		(0 << 3)

#define TCR_CKEG_FALLING	(1 << 3)

#define TCR_CKEG_BOTH		(2 << 3)

#define TCR_CKEG_MASK		(3 << 3)

/* Values 4 to 7 are channel-dependent */

#define TCR_TPSC_P1		(0 << 0)

#define TCR_TPSC_P4		(1 << 0)

#define TCR_TPSC_P16		(2 << 0)

#define TCR_TPSC_P64		(3 << 0)

#define TCR_TPSC_CH0_TCLKA	(4 << 0)

#define TCR_TPSC_CH0_TCLKB	(5 << 0)

#define TCR_TPSC_CH0_TCLKC	(6 << 0)

#define TCR_TPSC_CH0_TCLKD	(7 << 0)

#define TCR_TPSC_CH1_TCLKA	(4 << 0)

#define TCR_TPSC_CH1_TCLKB	(5 << 0)

#define TCR_TPSC_CH1_P256	(6 << 0)

#define TCR_TPSC_CH1_TCNT2	(7 << 0)

#define TCR_TPSC_CH2_TCLKA	(4 << 0)

#define TCR_TPSC_CH2_TCLKB	(5 << 0)

#define TCR_TPSC_CH2_TCLKC	(6 << 0)

#define TCR_TPSC_CH2_P1024	(7 << 0)

#define TCR_TPSC_CH34_P256	(4 << 0)

#define TCR_TPSC_CH34_P1024	(5 << 0)

#define TCR_TPSC_CH34_TCLKA	(6 << 0)

#define TCR_TPSC_CH34_TCLKB	(7 << 0)

#define TCR_TPSC_MASK		(7 << 0)



#define TMDR_BFE		(1 << 6)

#define TMDR_BFB		(1 << 5)

#define TMDR_BFA		(1 << 4)

#define TMDR_MD_NORMAL		(0 << 0)

#define TMDR_MD_PWM_1		(2 << 0)

#define TMDR_MD_PWM_2		(3 << 0)

#define TMDR_MD_PHASE_1		(4 << 0)

#define TMDR_MD_PHASE_2		(5 << 0)

#define TMDR_MD_PHASE_3		(6 << 0)

#define TMDR_MD_PHASE_4		(7 << 0)

#define TMDR_MD_PWM_SYNC	(8 << 0)

#define TMDR_MD_PWM_COMP_CREST	(13 << 0)

#define TMDR_MD_PWM_COMP_TROUGH	(14 << 0)

#define TMDR_MD_PWM_COMP_BOTH	(15 << 0)

#define TMDR_MD_MASK		(15 << 0)



#define TIOC_IOCH(n)		((n) << 4)

#define TIOC_IOCL(n)		((n) << 0)

#define TIOR_OC_RETAIN		(0 << 0)

#define TIOR_OC_0_CLEAR		(1 << 0)

#define TIOR_OC_0_SET		(2 << 0)

#define TIOR_OC_0_TOGGLE	(3 << 0)

#define TIOR_OC_1_CLEAR		(5 << 0)

#define TIOR_OC_1_SET		(6 << 0)

#define TIOR_OC_1_TOGGLE	(7 << 0)

#define TIOR_IC_RISING		(8 << 0)

#define TIOR_IC_FALLING		(9 << 0)

#define TIOR_IC_BOTH		(10 << 0)

#define TIOR_IC_TCNT		(12 << 0)

#define TIOR_MASK		(15 << 0)



#define TIER_TTGE		(1 << 7)

#define TIER_TTGE2		(1 << 6)

#define TIER_TCIEU		(1 << 5)

#define TIER_TCIEV		(1 << 4)

#define TIER_TGIED		(1 << 3)

#define TIER_TGIEC		(1 << 2)

#define TIER_TGIEB		(1 << 1)

#define TIER_TGIEA		(1 << 0)



#define TSR_TCFD		(1 << 7)

#define TSR_TCFU		(1 << 5)

#define TSR_TCFV		(1 << 4)

#define TSR_TGFD		(1 << 3)

#define TSR_TGFC		(1 << 2)

#define TSR_TGFB		(1 << 1)

#define TSR_TGFA		(1 << 0)



static unsigned long mtu2_reg_offs[] = {

	[TCR] = 0,

	[TMDR] = 1,
@@ -150,13 +232,17 @@ static int sh_mtu2_enable(struct sh_mtu2_channel *ch) 
	rate = clk_get_rate(ch->mtu->clk) / 64;

	periodic = (rate + HZ/2) / HZ;



	/* "Periodic Counter Operation" */

	sh_mtu2_write(ch, TCR, 0x23); /* TGRA clear, divide clock by 64 */

	sh_mtu2_write(ch, TIOR, 0);

	/*

	 * "Periodic Counter Operation"

	 * Clear on TGRA compare match, divide clock by 64.

	 */

	sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);

	sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) |

		      TIOC_IOCL(TIOR_OC_0_CLEAR));

	sh_mtu2_write(ch, TGR, periodic);

	sh_mtu2_write(ch, TCNT, 0);

	sh_mtu2_write(ch, TMDR, 0);

	sh_mtu2_write(ch, TIER, 0x01);

	sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL);

	sh_mtu2_write(ch, TIER, TIER_TGIEA);



	/* enable channel */

	sh_mtu2_start_stop_ch(ch, 1);
@@ -182,7 +268,7 @@ static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id) 


	/* acknowledge interrupt */

	sh_mtu2_read(ch, TSR);

	sh_mtu2_write(ch, TSR, 0xfe);

	sh_mtu2_write(ch, TSR, ~TSR_TGFA);



	/* notify clockevent layer */

	ch->ced.event_handler(&ch->ced);