Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f9675674 authored by Huang Rui's avatar Huang Rui Committed by Ingo Molnar
Browse files

x86/asm: Add MONITORX/MWAITX instruction support 



AMD Carrizo processors (Family 15h, Models 60h-6fh) added a new
feature called MWAITX (MWAIT with extensions) as an extension to
MONITOR/MWAIT.

This new instruction controls a configurable timer which causes
the core to exit wait state on timer expiration, in addition to
"normal" MWAIT condition of reading from a monitored VA.

Compared to MONITOR/MWAIT, there are minor differences in opcode
and input parameters:

MWAITX ECX[1]: enable timer if set
MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks ==
TSC. The software P0 frequency is the same as the TSC frequency.

                MWAIT                           MWAITX
opcode          0f 01 c9           |            0f 01 fb
ECX[0]                  value of RFLAGS.IF seen by instruction
ECX[1]          unused/#GP if set  |            enable timer if set
ECX[31:2]                     unused/#GP if set
EAX                           unused (reserve for hint)
EBX[31:0]       unused             |            max wait time (SW P0 == TSC)

                MONITOR                         MONITORX
opcode          0f 01 c8           |            0f 01 fa
EAX                     (logical) address to monitor
ECX                     #GP if not zero

Max timeout = EBX/(TSC frequency)

Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Aaron Lu <aaron.lu@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andreas Herrmann <herrmann.der.user@gmail.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Dirk Brandewie <dirk.j.brandewie@intel.com>
Cc: Fengguang Wu <fengguang.wu@intel.com>
Cc: Frédéric Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Josh Triplett <josh@joshtriplett.org>
Cc: Len Brown <lenb@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mike Galbraith <bitbucket@online.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Ross Zwisler <ross.zwisler@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Li <tony.li@amd.com>
Link: http://lkml.kernel.org/r/1439201994-28067-3-git-send-email-bp@alien8.de


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent f0a97af8

arch/x86/include/asm/cpufeature.h

+1 −0
Original line number Diff line number Diff line
@@ -176,6 +176,7 @@ 
#define X86_FEATURE_PERFCTR_NB  ( 6*32+24) /* NB performance counter extensions */

#define X86_FEATURE_BPEXT	(6*32+26) /* data breakpoint extension */

#define X86_FEATURE_PERFCTR_L2	( 6*32+28) /* L2 performance counter extensions */

#define X86_FEATURE_MWAITX	( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */



/*

 * Auxiliary flags: Linux defined - For features scattered in various

arch/x86/include/asm/mwait.h

+45 −0
Original line number Diff line number Diff line
@@ -14,6 +14,9 @@ 
#define CPUID5_ECX_INTERRUPT_BREAK	0x2



#define MWAIT_ECX_INTERRUPT_BREAK	0x1

#define MWAITX_ECX_TIMER_ENABLE		BIT(1)

#define MWAITX_MAX_LOOPS		((u32)-1)

#define MWAITX_DISABLE_CSTATES		0xf



static inline void __monitor(const void *eax, unsigned long ecx,

			     unsigned long edx)
@@ -23,6 +26,14 @@ static inline void __monitor(const void *eax, unsigned long ecx, 
		     :: "a" (eax), "c" (ecx), "d"(edx));

}



static inline void __monitorx(const void *eax, unsigned long ecx,

			      unsigned long edx)

{

	/* "monitorx %eax, %ecx, %edx;" */

	asm volatile(".byte 0x0f, 0x01, 0xfa;"

		     :: "a" (eax), "c" (ecx), "d"(edx));

}



static inline void __mwait(unsigned long eax, unsigned long ecx)

{

	/* "mwait %eax, %ecx;" */
@@ -30,6 +41,40 @@ static inline void __mwait(unsigned long eax, unsigned long ecx) 
		     :: "a" (eax), "c" (ecx));

}



/*

 * MWAITX allows for a timer expiration to get the core out a wait state in

 * addition to the default MWAIT exit condition of a store appearing at a

 * monitored virtual address.

 *

 * Registers:

 *

 * MWAITX ECX[1]: enable timer if set

 * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0

 * frequency is the same as the TSC frequency.

 *

 * Below is a comparison between MWAIT and MWAITX on AMD processors:

 *

 *                 MWAIT                           MWAITX

 * opcode          0f 01 c9           |            0f 01 fb

 * ECX[0]                  value of RFLAGS.IF seen by instruction

 * ECX[1]          unused/#GP if set  |            enable timer if set

 * ECX[31:2]                     unused/#GP if set

 * EAX                           unused (reserve for hint)

 * EBX[31:0]       unused             |            max wait time (P0 clocks)

 *

 *                 MONITOR                         MONITORX

 * opcode          0f 01 c8           |            0f 01 fa

 * EAX                     (logical) address to monitor

 * ECX                     #GP if not zero

 */

static inline void __mwaitx(unsigned long eax, unsigned long ebx,

			    unsigned long ecx)

{

	/* "mwaitx %eax, %ebx, %ecx;" */

	asm volatile(".byte 0x0f, 0x01, 0xfb;"

		     :: "a" (eax), "b" (ebx), "c" (ecx));

}



static inline void __sti_mwait(unsigned long eax, unsigned long ecx)

{

	trace_hardirqs_on();