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Commit f84c39da authored by Liu Dave-r63238's avatar Liu Dave-r63238 Committed by Paul Mackerras
Browse files

[POWERPC] Fix the UCC rx/tx clock of QE 



MPC8323EMDS board ethernet interface with RMII uses the CLK16 divisor
for the rx and tx clock, but the ucc_set_qe_mux_rxtx() function doesn't
handle the CLK16 setting of the CMXUCR3 and CMXUCR4 registers.  This
fixes it.

Signed-off-by: default avatarDave Liu <daveliu@freescale.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent b910ecf6

arch/powerpc/sysdev/qe_lib/ucc.c

+2 −0
Original line number Diff line number Diff line
@@ -207,6 +207,7 @@ int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode) 
		case QE_CLK18:	source = 8; break;

		case QE_CLK7:	source = 9; break;

		case QE_CLK8:	source = 10; break;

		case QE_CLK16:	source = 11; break;

		default:	source = -1; break;

		}

		break;
@@ -222,6 +223,7 @@ int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode) 
		case QE_CLK22:	source = 8; break;

		case QE_CLK7:	source = 9; break;

		case QE_CLK8:	source = 10; break;

		case QE_CLK16:	source = 11; break;

		default: 	source = -1; break;

		}

		break;