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Commit f82b3ddc authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: DCE5 atom SetPixelClock updates 



Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 881dd74e

drivers/gpu/drm/radeon/atombios_crtc.c

+28 −3
Original line number Diff line number Diff line
@@ -673,9 +673,14 @@ union set_pixel_clock { 
	PIXEL_CLOCK_PARAMETERS_V2 v2;

	PIXEL_CLOCK_PARAMETERS_V3 v3;

	PIXEL_CLOCK_PARAMETERS_V5 v5;

	PIXEL_CLOCK_PARAMETERS_V6 v6;

};



static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)

/* on DCE5, make sure the voltage is high enough to support the

 * required disp clk.

 */

static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,

				    u32 dispclk)

{

	struct drm_device *dev = crtc->dev;

	struct radeon_device *rdev = dev->dev_private;
@@ -698,9 +703,16 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc) 
			 * SetPixelClock provides the dividers

			 */

			args.v5.ucCRTC = ATOM_CRTC_INVALID;

			args.v5.usPixelClock = rdev->clock.default_dispclk;

			args.v5.usPixelClock = dispclk;

			args.v5.ucPpll = ATOM_DCPLL;

			break;

		case 6:

			/* if the default dcpll clock is specified,

			 * SetPixelClock provides the dividers

			 */

			args.v6.ulDispEngClkFreq = dispclk;

			args.v6.ucPpll = ATOM_DCPLL;

			break;

		default:

			DRM_ERROR("Unknown table version %d %d\n", frev, crev);

			return;
@@ -784,6 +796,18 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc, 
			args.v5.ucEncoderMode = encoder_mode;

			args.v5.ucPpll = pll_id;

			break;

		case 6:

			args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id;

			args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10);

			args.v6.ucRefDiv = ref_div;

			args.v6.usFbDiv = cpu_to_le16(fb_div);

			args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);

			args.v6.ucPostDiv = post_div;

			args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */

			args.v6.ucTransmitterID = encoder_id;

			args.v6.ucEncoderMode = encoder_mode;

			args.v6.ucPpll = pll_id;

			break;

		default:

			DRM_ERROR("Unknown table version %d %d\n", frev, crev);

			return;
@@ -1377,7 +1401,8 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, 
								   rdev->clock.default_dispclk);

		if (ss_enabled)

			atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);

		atombios_crtc_set_dcpll(crtc);

		/* XXX: DCE5, make sure voltage, dispclk is high enough */

		atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);

		if (ss_enabled)

			atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);

	}

drivers/gpu/drm/radeon/radeon_atombios.c

+19 −6
Original line number Diff line number Diff line
@@ -1086,6 +1086,7 @@ union firmware_info { 
	ATOM_FIRMWARE_INFO_V1_3 info_13;

	ATOM_FIRMWARE_INFO_V1_4 info_14;

	ATOM_FIRMWARE_INFO_V2_1 info_21;

	ATOM_FIRMWARE_INFO_V2_2 info_22;

};



bool radeon_atom_get_clock_info(struct drm_device *dev)
@@ -1160,6 +1161,10 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) 
		*p2pll = *p1pll;



		/* system clock */

		if (ASIC_IS_DCE4(rdev))

			spll->reference_freq =

				le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);

		else

			spll->reference_freq =

				le16_to_cpu(firmware_info->info.usReferenceClock);

		spll->reference_div = 0;
@@ -1183,6 +1188,10 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) 
		    le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);



		/* memory clock */

		if (ASIC_IS_DCE4(rdev))

			mpll->reference_freq =

				le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);

		else

			mpll->reference_freq =

				le16_to_cpu(firmware_info->info.usReferenceClock);

		mpll->reference_div = 0;
@@ -1213,8 +1222,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) 
		if (ASIC_IS_DCE4(rdev)) {

			rdev->clock.default_dispclk =

				le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);

			if (rdev->clock.default_dispclk == 0)

			if (rdev->clock.default_dispclk == 0) {

				if (ASIC_IS_DCE5(rdev))

					rdev->clock.default_dispclk = 54000; /* 540 Mhz */

				else

					rdev->clock.default_dispclk = 60000; /* 600 Mhz */

			}

			rdev->clock.dp_extclk =

				le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);

		}