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Commit f7d2974f authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.9.50 into android-4.9 



Changes in 4.9.50
	mtd: nand: mxc: Fix mxc_v1 ooblayout
	mtd: nand: qcom: fix read failure without complete bootchain
	mtd: nand: qcom: fix config error for BCH
	nvme-fabrics: generate spec-compliant UUID NQNs
	btrfs: resume qgroup rescan on rw remount
	selftests/x86/fsgsbase: Test selectors 1, 2, and 3
	mm/memory.c: fix mem_cgroup_oom_disable() call missing
	locktorture: Fix potential memory leak with rw lock test
	ALSA: msnd: Optimize / harden DSP and MIDI loops
	Bluetooth: Properly check L2CAP config option output buffer length
	ARM64: dts: marvell: armada-37xx: Fix GIC maintenance interrupt
	ARM: 8692/1: mm: abort uaccess retries upon fatal signal
	NFS: Fix 2 use after free issues in the I/O code
	NFS: Sync the correct byte range during synchronous writes
	xfs: XFS_IS_REALTIME_INODE() should be false if no rt device present
	Linux 4.9.50

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
parents 0268f76e 4ad5dcac

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 4

PATCHLEVEL = 9

SUBLEVEL = 49

SUBLEVEL = 50

EXTRAVERSION =

NAME = Roaring Lionus

arch/arm/mm/fault.c

+4 −1
Original line number Diff line number Diff line
@@ -314,8 +314,11 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) 
	 * signal first. We do not need to release the mmap_sem because

	 * it would already be released in __lock_page_or_retry in

	 * mm/filemap.c. */

	if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))

	if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) {

		if (!user_mode(regs))

			goto no_context;

		return 0;

	}



	/*

	 * Major/minor page fault accounting is only done on the

arch/arm64/boot/dts/marvell/armada-37xx.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -170,6 +170,7 @@ 
				interrupt-controller;

				reg = <0x1d00000 0x10000>, /* GICD */

				      <0x1d40000 0x40000>; /* GICR */

				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			};

		};

drivers/mtd/nand/mxc_nand.c

+4 −3
Original line number Diff line number Diff line
@@ -877,6 +877,8 @@ static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) 
	}

}



#define MXC_V1_ECCBYTES		5



static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section,

				struct mtd_oob_region *oobregion)

{
@@ -886,7 +888,7 @@ static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section, 
		return -ERANGE;



	oobregion->offset = (section * 16) + 6;

	oobregion->length = nand_chip->ecc.bytes;

	oobregion->length = MXC_V1_ECCBYTES;



	return 0;

}
@@ -908,8 +910,7 @@ static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section, 
			oobregion->length = 4;

		}

	} else {

		oobregion->offset = ((section - 1) * 16) +

				    nand_chip->ecc.bytes + 6;

		oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6;

		if (section < nand_chip->ecc.steps)

			oobregion->length = (section * 16) + 6 -

					    oobregion->offset;

drivers/mtd/nand/qcom_nandc.c

+13 −5
Original line number Diff line number Diff line
@@ -109,7 +109,11 @@ 
#define	READ_ADDR			0



/* NAND_DEV_CMD_VLD bits */

#define	READ_START_VLD			0

#define	READ_START_VLD			BIT(0)

#define	READ_STOP_VLD			BIT(1)

#define	WRITE_START_VLD			BIT(2)

#define	ERASE_START_VLD			BIT(3)

#define	SEQ_READ_START_VLD		BIT(4)



/* NAND_EBI2_ECC_BUF_CFG bits */

#define	NUM_STEPS			0
@@ -148,6 +152,10 @@ 
#define	FETCH_ID			0xb

#define	RESET_DEVICE			0xd



/* Default Value for NAND_DEV_CMD_VLD */

#define NAND_DEV_CMD_VLD_VAL		(READ_START_VLD | WRITE_START_VLD | \

					 ERASE_START_VLD | SEQ_READ_START_VLD)



/*

 * the NAND controller performs reads/writes with ECC in 516 byte chunks.

 * the driver calls the chunks 'step' or 'codeword' interchangeably
@@ -672,8 +680,7 @@ static int nandc_param(struct qcom_nand_host *host) 


	/* configure CMD1 and VLD for ONFI param probing */

	nandc_set_reg(nandc, NAND_DEV_CMD_VLD,

		      (nandc->vld & ~(1 << READ_START_VLD))

		      | 0 << READ_START_VLD);

		      (nandc->vld & ~READ_START_VLD));

	nandc_set_reg(nandc, NAND_DEV_CMD1,

		      (nandc->cmd1 & ~(0xFF << READ_ADDR))

		      | NAND_CMD_PARAM << READ_ADDR);
@@ -1893,7 +1900,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host) 
				| wide_bus << WIDE_FLASH

				| 1 << DEV0_CFG1_ECC_DISABLE;



	host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE

	host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE

				| 0 << ECC_SW_RESET

				| host->cw_data << ECC_NUM_DATA_BYTES

				| 1 << ECC_FORCE_CLK_OPEN
@@ -1972,13 +1979,14 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) 
{

	/* kill onenand */

	nandc_write(nandc, SFLASHC_BURST_CFG, 0);

	nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);



	/* enable ADM DMA */

	nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);



	/* save the original values of these registers */

	nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);

	nandc->vld = nandc_read(nandc, NAND_DEV_CMD_VLD);

	nandc->vld = NAND_DEV_CMD_VLD_VAL;



	return 0;

}