Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f69fb9c3 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
  agp/intel: support for new chip variant of IGDNG mobile
  drm/i915: Unref old_obj on get_fence_reg() error path
  drm/i915: increase default latency constant (v2 w/comment)
parents e07cccf4 07fb6111

drivers/char/agp/intel-agp.c

+7 −1
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ 
#define PCI_DEVICE_ID_INTEL_IGDNG_D_HB	    0x0040

#define PCI_DEVICE_ID_INTEL_IGDNG_D_IG	    0x0042

#define PCI_DEVICE_ID_INTEL_IGDNG_M_HB	    0x0044

#define PCI_DEVICE_ID_INTEL_IGDNG_MA_HB	    0x0062

#define PCI_DEVICE_ID_INTEL_IGDNG_M_IG	    0x0046



/* cover 915 and 945 variants */
@@ -81,7 +82,8 @@ 
		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB)

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB)



extern int agp_memory_reserved;
@@ -1216,6 +1218,7 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 
	case PCI_DEVICE_ID_INTEL_G41_HB:

	case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:

	case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:

	case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB:

		*gtt_offset = *gtt_size = MB(2);

		break;

	default:
@@ -2195,6 +2198,8 @@ static const struct intel_driver_description { 
	    "IGDNG/D", NULL, &intel_i965_driver },

	{ PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,

	    "IGDNG/M", NULL, &intel_i965_driver },

	{ PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,

	    "IGDNG/MA", NULL, &intel_i965_driver },

	{ 0, 0, 0, NULL, NULL, NULL }

};
@@ -2398,6 +2403,7 @@ static struct pci_device_id agp_intel_pci_table[] = { 
	ID(PCI_DEVICE_ID_INTEL_G41_HB),

	ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),

	ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),

	ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB),

	{ }

};

drivers/gpu/drm/i915/i915_gem.c

+9 −4
Original line number Diff line number Diff line
@@ -2267,8 +2267,6 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj) 
				    fence_list) {

			old_obj = old_obj_priv->obj;



			reg = &dev_priv->fence_regs[old_obj_priv->fence_reg];



			if (old_obj_priv->pin_count)

				continue;
@@ -2290,8 +2288,11 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj) 
			 */

			i915_gem_object_flush_gpu_write_domain(old_obj);

			ret = i915_gem_object_wait_rendering(old_obj);

			if (ret != 0)

			if (ret != 0) {

				drm_gem_object_unreference(old_obj);

				return ret;

			}



			break;

		}
@@ -2299,10 +2300,14 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj) 
		 * Zap this virtual mapping so we can set up a fence again

		 * for this object next time we need it.

		 */

		i915_gem_release_mmap(reg->obj);

		i915_gem_release_mmap(old_obj);



		i = old_obj_priv->fence_reg;

		reg = &dev_priv->fence_regs[i];



		old_obj_priv->fence_reg = I915_FENCE_REG_NONE;

		list_del_init(&old_obj_priv->fence_list);



		drm_gem_object_unreference(old_obj);

	}

drivers/gpu/drm/i915/intel_display.c

+15 −1
Original line number Diff line number Diff line
@@ -2005,7 +2005,21 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock, 
	return;

}



const static int latency_ns = 3000; /* default for non-igd platforms */

/*

 * Latency for FIFO fetches is dependent on several factors:

 *   - memory configuration (speed, channels)

 *   - chipset

 *   - current MCH state

 * It can be fairly high in some situations, so here we assume a fairly

 * pessimal value.  It's a tradeoff between extra memory fetches (if we

 * set this value too high, the FIFO will fetch frequently to stay full)

 * and power consumption (set it too low to save power and we might see

 * FIFO underruns and display "flicker").

 *

 * A value of 5us seems to be a good balance; safe for very low end

 * platforms but not overly aggressive on lower latency configs.

 */

const static int latency_ns = 5000;



static int intel_get_fifo_size(struct drm_device *dev, int plane)

{