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Commit f5d88f58 authored by Jiri Pirko's avatar Jiri Pirko Committed by David S. Miller
Browse files

mlxsw: reg: Add Switch FDB Notification register definition 



Add SFN register which is used to poll for newly added and aged-out FDB
entries.

Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 236033b3

drivers/net/ethernet/mellanox/mlxsw/reg.h

+101 −0
Original line number Diff line number Diff line
@@ -371,6 +371,105 @@ mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 
	*p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);

}



/* SFN - Switch FDB Notification Register

 * -------------------------------------------

 * The switch provides notifications on newly learned FDB entries and

 * aged out entries. The notifications can be polled by software.

 */

#define MLXSW_REG_SFN_ID 0x200B

#define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */

#define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */

#define MLXSW_REG_SFN_REC_MAX_COUNT 64

#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN +	\

			   MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)



static const struct mlxsw_reg_info mlxsw_reg_sfn = {

	.id = MLXSW_REG_SFN_ID,

	.len = MLXSW_REG_SFN_LEN,

};



/* reg_sfn_swid

 * Switch partition ID.

 * Access: Index

 */

MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);



/* reg_sfn_num_rec

 * Request: Number of learned notifications and aged-out notification

 * records requested.

 * Response: Number of notification records returned (must be smaller

 * than or equal to the value requested)

 * Ranges 0..64

 * Access: OP

 */

MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);



static inline void mlxsw_reg_sfn_pack(char *payload)

{

	MLXSW_REG_ZERO(sfn, payload);

	mlxsw_reg_sfn_swid_set(payload, 0);

	mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);

}



/* reg_sfn_rec_swid

 * Switch partition ID.

 * Access: RO

 */

MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,

		     MLXSW_REG_SFN_REC_LEN, 0x00, false);



enum mlxsw_reg_sfn_rec_type {

	/* MAC addresses learned on a regular port. */

	MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,

	/* Aged-out MAC address on a regular port */

	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,

};



/* reg_sfn_rec_type

 * Notification record type.

 * Access: RO

 */

MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,

		     MLXSW_REG_SFN_REC_LEN, 0x00, false);



/* reg_sfn_rec_mac

 * MAC address.

 * Access: RO

 */

MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,

		       MLXSW_REG_SFN_REC_LEN, 0x02);



/* reg_sfd_mac_sub_port

 * VEPA channel on the local port.

 * 0 if multichannel VEPA is not enabled.

 * Access: RO

 */

MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,

		     MLXSW_REG_SFN_REC_LEN, 0x08, false);



/* reg_sfd_mac_fid

 * Filtering identifier.

 * Access: RO

 */

MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,

		     MLXSW_REG_SFN_REC_LEN, 0x08, false);



/* reg_sfd_mac_system_port

 * Unique port identifier for the final destination of the packet.

 * Access: RO

 */

MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,

		     MLXSW_REG_SFN_REC_LEN, 0x0C, false);



static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,

					    char *mac, u16 *p_vid,

					    u8 *p_local_port)

{

	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);

	*p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);

	*p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);

}



/* SPMS - Switch Port MSTP/RSTP State Register

 * -------------------------------------------

 * Configures the spanning tree state of a physical port.
@@ -1467,6 +1566,8 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id) 
		return "SSPR";

	case MLXSW_REG_SFD_ID:

		return "SFD";

	case MLXSW_REG_SFN_ID:

		return "SFN";

	case MLXSW_REG_SPMS_ID:

		return "SPMS";

	case MLXSW_REG_SFGC_ID: