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Commit f55df0d6 authored by Maxime Ripard's avatar Maxime Ripard Committed by Nicolas Ferre
Browse files

ARM: at91: Remove rstc and shdwc headers 



These headers used to provide an "API" to access the rstc and shdwc registers.
Now that no-one uses this API anymore, we can safely remove those.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent 351a4ffe

arch/arm/mach-at91/at91_rstc.h

deleted100644 → 0
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/*

 * arch/arm/mach-at91/include/mach/at91_rstc.h

 *

 * Copyright (C) 2007 Andrew Victor

 * Copyright (C) 2007 Atmel Corporation.

 *

 * Reset Controller (RSTC) - System peripherals regsters.

 * Based on AT91SAM9261 datasheet revision D.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef AT91_RSTC_H

#define AT91_RSTC_H



#ifndef __ASSEMBLY__

extern void __iomem *at91_rstc_base;



#define at91_rstc_read(field) \

	__raw_readl(at91_rstc_base + field)



#define at91_rstc_write(field, value) \

	__raw_writel(value, at91_rstc_base + field)

#else

.extern at91_rstc_base

#endif



#define AT91_RSTC_CR		0x00			/* Reset Controller Control Register */

#define		AT91_RSTC_PROCRST	(1 << 0)		/* Processor Reset */

#define		AT91_RSTC_PERRST	(1 << 2)		/* Peripheral Reset */

#define		AT91_RSTC_EXTRST	(1 << 3)		/* External Reset */

#define		AT91_RSTC_KEY		(0xa5 << 24)		/* KEY Password */



#define AT91_RSTC_SR		0x04			/* Reset Controller Status Register */

#define		AT91_RSTC_URSTS		(1 << 0)		/* User Reset Status */

#define		AT91_RSTC_RSTTYP	(7 << 8)		/* Reset Type */

#define			AT91_RSTC_RSTTYP_GENERAL	(0 << 8)

#define			AT91_RSTC_RSTTYP_WAKEUP		(1 << 8)

#define			AT91_RSTC_RSTTYP_WATCHDOG	(2 << 8)

#define			AT91_RSTC_RSTTYP_SOFTWARE	(3 << 8)

#define			AT91_RSTC_RSTTYP_USER	(4 << 8)

#define		AT91_RSTC_NRSTL		(1 << 16)		/* NRST Pin Level */

#define		AT91_RSTC_SRCMP		(1 << 17)		/* Software Reset Command in Progress */



#define AT91_RSTC_MR		0x08			/* Reset Controller Mode Register */

#define		AT91_RSTC_URSTEN	(1 << 0)		/* User Reset Enable */

#define		AT91_RSTC_URSTIEN	(1 << 4)		/* User Reset Interrupt Enable */

#define		AT91_RSTC_ERSTL		(0xf << 8)		/* External Reset Length */



#endif

arch/arm/mach-at91/at91_shdwc.h

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/*

 * arch/arm/mach-at91/include/mach/at91_shdwc.h

 *

 * Copyright (C) 2007 Andrew Victor

 * Copyright (C) 2007 Atmel Corporation.

 *

 * Shutdown Controller (SHDWC) - System peripherals regsters.

 * Based on AT91SAM9261 datasheet revision D.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef AT91_SHDWC_H

#define AT91_SHDWC_H



#ifndef __ASSEMBLY__

extern void __iomem *at91_shdwc_base;



#define at91_shdwc_read(field) \

	__raw_readl(at91_shdwc_base + field)



#define at91_shdwc_write(field, value) \

	__raw_writel(value, at91_shdwc_base + field)

#endif



#define AT91_SHDW_CR		0x00			/* Shut Down Control Register */

#define		AT91_SHDW_SHDW		(1    << 0)		/* Shut Down command */

#define		AT91_SHDW_KEY		(0xa5 << 24)		/* KEY Password */



#define AT91_SHDW_MR		0x04			/* Shut Down Mode Register */

#define		AT91_SHDW_WKMODE0	(3 << 0)		/* Wake-up 0 Mode Selection */

#define			AT91_SHDW_WKMODE0_NONE		0

#define			AT91_SHDW_WKMODE0_HIGH		1

#define			AT91_SHDW_WKMODE0_LOW		2

#define			AT91_SHDW_WKMODE0_ANYLEVEL	3

#define		AT91_SHDW_CPTWK0_MAX	0xf			/* Maximum Counter On Wake Up 0 */

#define		AT91_SHDW_CPTWK0	(AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */

#define			AT91_SHDW_CPTWK0_(x)	((x) << 4)

#define		AT91_SHDW_RTTWKEN	(1   << 16)		/* Real Time Timer Wake-up Enable */

#define		AT91_SHDW_RTCWKEN	(1   << 17)		/* Real Time Clock Wake-up Enable */



#define AT91_SHDW_SR		0x08			/* Shut Down Status Register */

#define		AT91_SHDW_WAKEUP0	(1 <<  0)		/* Wake-up 0 Status */

#define		AT91_SHDW_RTTWK		(1 << 16)		/* Real-time Timer Wake-up */

#define		AT91_SHDW_RTCWK		(1 << 17)		/* Real-time Clock Wake-up [SAM9RL] */



#endif

arch/arm/mach-at91/at91sam9260.c

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@@ -25,7 +25,6 @@ 
#include <mach/hardware.h>

#include <mach/hardware.h>





#include "at91_aic.h"

#include "at91_aic.h"

#include "at91_rstc.h"

#include "soc.h"

#include "soc.h"

#include "generic.h"

#include "generic.h"

#include "sam9_smc.h"

#include "sam9_smc.h"

arch/arm/mach-at91/at91sam9261.c

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Original line number Original line Diff line number Diff line
@@ -24,7 +24,6 @@ 
#include <mach/hardware.h>

#include <mach/hardware.h>





#include "at91_aic.h"

#include "at91_aic.h"

#include "at91_rstc.h"

#include "soc.h"

#include "soc.h"

#include "generic.h"

#include "generic.h"

#include "sam9_smc.h"

#include "sam9_smc.h"

arch/arm/mach-at91/at91sam9263.c

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@@ -23,7 +23,6 @@ 
#include <mach/hardware.h>

#include <mach/hardware.h>





#include "at91_aic.h"

#include "at91_aic.h"

#include "at91_rstc.h"

#include "soc.h"

#include "soc.h"

#include "generic.h"

#include "generic.h"

#include "sam9_smc.h"

#include "sam9_smc.h"