Loading arch/arm/Makefile +1 −1 Original line number Diff line number Diff line Loading @@ -96,7 +96,7 @@ tune-$(CONFIG_CPU_V6K) =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm) tune-y := $(tune-y) ifeq ($(CONFIG_AEABI),y) CFLAGS_ABI :=-mabi=aapcs-linux -mno-thumb-interwork CFLAGS_ABI :=-mabi=aapcs-linux -mno-thumb-interwork -mfpu=vfp else CFLAGS_ABI :=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,) endif Loading arch/arm/include/asm/io.h +6 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,12 @@ #define isa_page_to_bus page_to_phys #define isa_bus_to_virt phys_to_virt /* * Atomic MMIO-wide IO modify */ extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set); extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set); /* * Generic IO read/write. These perform native-endian accesses. Note * that some architectures will want to re-define __raw_{read,write}w. Loading arch/arm/kernel/entry-armv.S +2 −0 Original line number Diff line number Diff line Loading @@ -451,9 +451,11 @@ __und_usr_thumb: .arch armv6t2 #endif 2: ldrht r5, [r4] ARM_BE8(rev16 r5, r5) @ little endian instruction cmp r5, #0xe800 @ 32bit instruction if xx != 0 blo __und_usr_fault_16 @ 16bit undefined instruction 3: ldrht r0, [r2] ARM_BE8(rev16 r0, r0) @ little endian instruction add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update orr r0, r0, r5, lsl #16 Loading arch/arm/kernel/head.S +2 −1 Original line number Diff line number Diff line Loading @@ -52,7 +52,8 @@ .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE .macro pgtbl, rd, phys add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE add \rd, \phys, #TEXT_OFFSET sub \rd, \rd, #PG_DIR_SIZE .endm /* Loading arch/arm/kernel/io.c +35 −0 Original line number Diff line number Diff line #include <linux/export.h> #include <linux/types.h> #include <linux/io.h> #include <linux/spinlock.h> static DEFINE_RAW_SPINLOCK(__io_lock); /* * Generic atomic MMIO modify. * * Allows thread-safe access to registers shared by unrelated subsystems. * The access is protected by a single MMIO-wide lock. */ void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set) { unsigned long flags; u32 value; raw_spin_lock_irqsave(&__io_lock, flags); value = readl_relaxed(reg) & ~mask; value |= (set & mask); writel_relaxed(value, reg); raw_spin_unlock_irqrestore(&__io_lock, flags); } EXPORT_SYMBOL(atomic_io_modify_relaxed); void atomic_io_modify(void __iomem *reg, u32 mask, u32 set) { unsigned long flags; u32 value; raw_spin_lock_irqsave(&__io_lock, flags); value = readl_relaxed(reg) & ~mask; value |= (set & mask); writel(value, reg); raw_spin_unlock_irqrestore(&__io_lock, flags); } EXPORT_SYMBOL(atomic_io_modify); /* * Copy data from IO memory space to "real" memory space. Loading Loading
arch/arm/Makefile +1 −1 Original line number Diff line number Diff line Loading @@ -96,7 +96,7 @@ tune-$(CONFIG_CPU_V6K) =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm) tune-y := $(tune-y) ifeq ($(CONFIG_AEABI),y) CFLAGS_ABI :=-mabi=aapcs-linux -mno-thumb-interwork CFLAGS_ABI :=-mabi=aapcs-linux -mno-thumb-interwork -mfpu=vfp else CFLAGS_ABI :=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,) endif Loading
arch/arm/include/asm/io.h +6 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,12 @@ #define isa_page_to_bus page_to_phys #define isa_bus_to_virt phys_to_virt /* * Atomic MMIO-wide IO modify */ extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set); extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set); /* * Generic IO read/write. These perform native-endian accesses. Note * that some architectures will want to re-define __raw_{read,write}w. Loading
arch/arm/kernel/entry-armv.S +2 −0 Original line number Diff line number Diff line Loading @@ -451,9 +451,11 @@ __und_usr_thumb: .arch armv6t2 #endif 2: ldrht r5, [r4] ARM_BE8(rev16 r5, r5) @ little endian instruction cmp r5, #0xe800 @ 32bit instruction if xx != 0 blo __und_usr_fault_16 @ 16bit undefined instruction 3: ldrht r0, [r2] ARM_BE8(rev16 r0, r0) @ little endian instruction add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update orr r0, r0, r5, lsl #16 Loading
arch/arm/kernel/head.S +2 −1 Original line number Diff line number Diff line Loading @@ -52,7 +52,8 @@ .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE .macro pgtbl, rd, phys add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE add \rd, \phys, #TEXT_OFFSET sub \rd, \rd, #PG_DIR_SIZE .endm /* Loading
arch/arm/kernel/io.c +35 −0 Original line number Diff line number Diff line #include <linux/export.h> #include <linux/types.h> #include <linux/io.h> #include <linux/spinlock.h> static DEFINE_RAW_SPINLOCK(__io_lock); /* * Generic atomic MMIO modify. * * Allows thread-safe access to registers shared by unrelated subsystems. * The access is protected by a single MMIO-wide lock. */ void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set) { unsigned long flags; u32 value; raw_spin_lock_irqsave(&__io_lock, flags); value = readl_relaxed(reg) & ~mask; value |= (set & mask); writel_relaxed(value, reg); raw_spin_unlock_irqrestore(&__io_lock, flags); } EXPORT_SYMBOL(atomic_io_modify_relaxed); void atomic_io_modify(void __iomem *reg, u32 mask, u32 set) { unsigned long flags; u32 value; raw_spin_lock_irqsave(&__io_lock, flags); value = readl_relaxed(reg) & ~mask; value |= (set & mask); writel(value, reg); raw_spin_unlock_irqrestore(&__io_lock, flags); } EXPORT_SYMBOL(atomic_io_modify); /* * Copy data from IO memory space to "real" memory space. Loading