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Commit f4b89764 authored by Linus Walleij's avatar Linus Walleij Committed by Vinod Koul
Browse files

dmaengine/ste_dma40: use AMBA PrimeCell helper macros 



The DMA40 is not a PrimeCell from ARM, but it still use the same
ID registers. So let's utilize the existing macros in the
PrimeCell header to identify manufacturer and revision of the IP
block instead of reinventing the wheel.

Cc: Robert Marklund <robert.marklund@stericsson.com>
Cc: Per Forlin <per.forlin@linaro.org>
Cc: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent 79ca7ec3

drivers/dma/ste_dma40.c

+26 −46
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/amba/bus.h>



#include <plat/ste_dma40.h>
@@ -44,9 +45,6 @@ 
#define D40_ALLOC_PHY		(1 << 30)

#define D40_ALLOC_LOG_FREE	0



/* Hardware designer of the block */

#define D40_HW_DESIGNER 0x8



/**

 * enum 40_command - The different commands and/or statuses.

 *
@@ -2525,25 +2523,6 @@ static int __init d40_phy_res_init(struct d40_base *base) 


static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)

{

	static const struct d40_reg_val dma_id_regs[] = {

		/* Peripheral Id */

		{ .reg = D40_DREG_PERIPHID0, .val = 0x0040},

		{ .reg = D40_DREG_PERIPHID1, .val = 0x0000},

		/*

		 * D40_DREG_PERIPHID2 Depends on HW revision:

		 *  DB8500ed has 0x0008,

		 *  ? has 0x0018,

		 *  DB8500v1 has 0x0028

		 *  DB8500v2 has 0x0038

		 */

		{ .reg = D40_DREG_PERIPHID3, .val = 0x0000},



		/* PCell Id */

		{ .reg = D40_DREG_CELLID0, .val = 0x000d},

		{ .reg = D40_DREG_CELLID1, .val = 0x00f0},

		{ .reg = D40_DREG_CELLID2, .val = 0x0005},

		{ .reg = D40_DREG_CELLID3, .val = 0x00b1}

	};

	struct stedma40_platform_data *plat_data;

	struct clk *clk = NULL;

	void __iomem *virtbase = NULL;
@@ -2552,8 +2531,9 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) 
	int num_log_chans = 0;

	int num_phy_chans;

	int i;

	u32 val;

	u32 rev;

	u32 pid;

	u32 cid;

	u8 rev;



	clk = clk_get(&pdev->dev, NULL);
@@ -2577,32 +2557,32 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) 
	if (!virtbase)

		goto failure;



	/* HW version check */

	for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {

		if (dma_id_regs[i].val !=

		    readl(virtbase + dma_id_regs[i].reg)) {

			d40_err(&pdev->dev,

				"Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",

				dma_id_regs[i].val,

				dma_id_regs[i].reg,

				readl(virtbase + dma_id_regs[i].reg));

	/* This is just a regular AMBA PrimeCell ID actually */

	for (pid = 0, i = 0; i < 4; i++)

		pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)

			& 255) << (i * 8);

	for (cid = 0, i = 0; i < 4; i++)

		cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)

			& 255) << (i * 8);



	if (cid != AMBA_CID) {

		d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");

		goto failure;

	}

	}



	/* Get silicon revision and designer */

	val = readl(virtbase + D40_DREG_PERIPHID2);



	if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=

	    D40_HW_DESIGNER) {

	if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {

		d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",

			val & D40_DREG_PERIPHID2_DESIGNER_MASK,

			D40_HW_DESIGNER);

			AMBA_MANF_BITS(pid),

			AMBA_VENDOR_ST);

		goto failure;

	}



	rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>

		D40_DREG_PERIPHID2_REV_POS;

	/*

	 * HW revision:

	 * DB8500ed has revision 0

	 * ? has revision 1

	 * DB8500v1 has revision 2

	 * DB8500v2 has revision 3

	 */

	rev = AMBA_REV_BITS(pid);



	/* The number of physical channels on this HW */

	num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;

drivers/dma/ste_dma40_ll.h

+0 −3
Original line number Diff line number Diff line
@@ -184,9 +184,6 @@ 
#define D40_DREG_PERIPHID0	0xFE0

#define D40_DREG_PERIPHID1	0xFE4

#define D40_DREG_PERIPHID2	0xFE8

#define D40_DREG_PERIPHID2_REV_POS 4

#define D40_DREG_PERIPHID2_REV_MASK (0xf << D40_DREG_PERIPHID2_REV_POS)

#define D40_DREG_PERIPHID2_DESIGNER_MASK 0xf

#define D40_DREG_PERIPHID3	0xFEC

#define D40_DREG_CELLID0	0xFF0

#define D40_DREG_CELLID1	0xFF4