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Commit f4254a2b authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/dce4+: set a more reasonable cursor watermark 



Set a more reasonable default cursor watermark. The
recommended default value is 4.  This should reduce
urgency requests to the MC form the display hw.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3d61bd42

drivers/gpu/drm/radeon/radeon_cursor.c

+4 −2
Original line number Original line Diff line number Diff line
@@ -67,7 +67,8 @@ static void radeon_hide_cursor(struct drm_crtc *crtc) 




	if (ASIC_IS_DCE4(rdev)) {

	if (ASIC_IS_DCE4(rdev)) {

		WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);

		WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);

		WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));

		WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |

		       EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));

	} else if (ASIC_IS_AVIVO(rdev)) {

	} else if (ASIC_IS_AVIVO(rdev)) {

		WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);

		WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);

		WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));

		WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
@@ -94,7 +95,8 @@ static void radeon_show_cursor(struct drm_crtc *crtc) 
	if (ASIC_IS_DCE4(rdev)) {

	if (ASIC_IS_DCE4(rdev)) {

		WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);

		WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);

		WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |

		WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |

		       EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));

		       EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |

		       EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));

	} else if (ASIC_IS_AVIVO(rdev)) {

	} else if (ASIC_IS_AVIVO(rdev)) {

		WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);

		WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);

		WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |

		WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |