Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f3fc4884 authored by Francisco Jerez's avatar Francisco Jerez Committed by Daniel Vetter
Browse files

drm/i915/hsw: Disable L3 caching of atomic memory operations.



Otherwise using any atomic memory operation will lock up the GPU due
to a Haswell hardware bug.

v2: Use the _MASKED_BIT_ENABLE macro.  Drop drm parameter definition.

Signed-off-by: default avatarFrancisco Jerez <currojerez@riseup.net>
Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: <stable@vger.kernel.org>
[danvet: Fix checkpatch fail.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 671952a2
Loading
Loading
Loading
Loading
+6 −0
Original line number Diff line number Diff line
@@ -3881,6 +3881,9 @@
#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)

#define HSW_SCRATCH1				0xb038
#define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1<<27)

#define HSW_FUSE_STRAP		0x42014
#define  HSW_CDCLK_LIMIT	(1 << 24)

@@ -4728,6 +4731,9 @@
#define GEN7_ROW_CHICKEN2_GT2		0xf4f4
#define   DOP_CLOCK_GATING_DISABLE	(1<<0)

#define HSW_ROW_CHICKEN3		0xe49c
#define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)

#define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)
#define INTEL_AUDIO_DEVCL		0x808629FB
#define INTEL_AUDIO_DEVBLC		0x80862801
+5 −0
Original line number Diff line number Diff line
@@ -4953,6 +4953,11 @@ static void haswell_init_clock_gating(struct drm_device *dev)
	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
			GEN7_WA_L3_CHICKEN_MODE);

	/* L3 caching of data atomics doesn't work -- disable it. */
	I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
	I915_WRITE(HSW_ROW_CHICKEN3,
		   _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));

	/* This is required by WaCatErrorRejectionIssue:hsw */
	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |