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Commit f3a71df0 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: fix 2D tiling CS support on EG/CM 

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=43191



Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 392e3722

drivers/gpu/drm/radeon/evergreen_cs.c

+123 −26
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ struct evergreen_cs_track { 
	u32			group_size;

	u32			nbanks;

	u32			npipes;

	u32			row_size;

	/* value we track */

	u32			nsamples;

	u32			cb_color_base_last[12];
@@ -77,6 +78,44 @@ struct evergreen_cs_track { 
	struct radeon_bo	*db_s_write_bo;

};



static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)

{

	if (tiling_flags & RADEON_TILING_MACRO)

		return ARRAY_2D_TILED_THIN1;

	else if (tiling_flags & RADEON_TILING_MICRO)

		return ARRAY_1D_TILED_THIN1;

	else

		return ARRAY_LINEAR_GENERAL;

}



static u32 evergreen_cs_get_num_banks(u32 nbanks)

{

	switch (nbanks) {

	case 2:

		return ADDR_SURF_2_BANK;

	case 4:

		return ADDR_SURF_4_BANK;

	case 8:

	default:

		return ADDR_SURF_8_BANK;

	case 16:

		return ADDR_SURF_16_BANK;

	}

}



static u32 evergreen_cs_get_tile_split(u32 row_size)

{

	switch (row_size) {

	case 1:

	default:

		return ADDR_SURF_TILE_SPLIT_1KB;

	case 2:

		return ADDR_SURF_TILE_SPLIT_2KB;

	case 4:

		return ADDR_SURF_TILE_SPLIT_4KB;

	}

}



static void evergreen_cs_track_init(struct evergreen_cs_track *track)

{

	int i;
@@ -490,12 +529,11 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
			}

			ib[idx] &= ~Z_ARRAY_MODE(0xf);

			track->db_z_info &= ~Z_ARRAY_MODE(0xf);

			ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));

			track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));

			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {

				ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);

				track->db_z_info |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);

			} else {

				ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);

				track->db_z_info |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);

				ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));

				ib[idx] |= DB_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));

			}

		}

		break;
@@ -618,13 +656,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
						"0x%04X\n", reg);

				return -EINVAL;

			}

			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {

				ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);

				track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);

			} else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {

				ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);

				track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);

			}

			ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));

			track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));

		}

		break;

	case CB_COLOR8_INFO:
@@ -640,13 +673,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
						"0x%04X\n", reg);

				return -EINVAL;

			}

			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {

				ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);

				track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);

			} else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {

				ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);

				track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);

			}

			ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));

			track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));

		}

		break;

	case CB_COLOR0_PITCH:
@@ -701,6 +729,16 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
	case CB_COLOR9_ATTRIB:

	case CB_COLOR10_ATTRIB:

	case CB_COLOR11_ATTRIB:

		r = evergreen_cs_packet_next_reloc(p, &reloc);

		if (r) {

			dev_warn(p->dev, "bad SET_CONTEXT_REG "

					"0x%04X\n", reg);

			return -EINVAL;

		}

		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {

			ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));

			ib[idx] |= CB_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));

		}

		break;

	case CB_COLOR0_DIM:

	case CB_COLOR1_DIM:
@@ -1318,10 +1356,14 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, 
				}

				ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

				if (!p->keep_tiling_flags) {

					if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)

						ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1);

					else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)

						ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);

					ib[idx+1+(i*8)+1] |=

						TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));

					if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {

						ib[idx+1+(i*8)+6] |=

							TEX_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));

						ib[idx+1+(i*8)+7] |=

							TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));

					}

				}

				texture = reloc->robj;

				/* tex mip base */
@@ -1422,6 +1464,7 @@ int evergreen_cs_parse(struct radeon_cs_parser *p) 
{

	struct radeon_cs_packet pkt;

	struct evergreen_cs_track *track;

	u32 tmp;

	int r;



	if (p->track == NULL) {
@@ -1430,9 +1473,63 @@ int evergreen_cs_parse(struct radeon_cs_parser *p) 
		if (track == NULL)

			return -ENOMEM;

		evergreen_cs_track_init(track);

		track->npipes = p->rdev->config.evergreen.tiling_npipes;

		track->nbanks = p->rdev->config.evergreen.tiling_nbanks;

		track->group_size = p->rdev->config.evergreen.tiling_group_size;

		if (p->rdev->family >= CHIP_CAYMAN)

			tmp = p->rdev->config.cayman.tile_config;

		else

			tmp = p->rdev->config.evergreen.tile_config;



		switch (tmp & 0xf) {

		case 0:

			track->npipes = 1;

			break;

		case 1:

		default:

			track->npipes = 2;

			break;

		case 2:

			track->npipes = 4;

			break;

		case 3:

			track->npipes = 8;

			break;

		}



		switch ((tmp & 0xf0) >> 4) {

		case 0:

			track->nbanks = 4;

			break;

		case 1:

		default:

			track->nbanks = 8;

			break;

		case 2:

			track->nbanks = 16;

			break;

		}



		switch ((tmp & 0xf00) >> 8) {

		case 0:

			track->group_size = 256;

			break;

		case 1:

		default:

			track->group_size = 512;

			break;

		}



		switch ((tmp & 0xf000) >> 12) {

		case 0:

			track->row_size = 1;

			break;

		case 1:

		default:

			track->row_size = 2;

			break;

		case 2:

			track->row_size = 4;

			break;

		}



		p->track = track;

	}

	do {

drivers/gpu/drm/radeon/evergreend.h

+31 −0
Original line number Diff line number Diff line
@@ -899,6 +899,10 @@ 
#define DB_HTILE_DATA_BASE				0x28014

#define DB_Z_INFO					0x28040

#       define Z_ARRAY_MODE(x)                          ((x) << 4)

#       define DB_TILE_SPLIT(x)                         (((x) & 0x7) << 8)

#       define DB_NUM_BANKS(x)                          (((x) & 0x3) << 12)

#       define DB_BANK_WIDTH(x)                         (((x) & 0x3) << 16)

#       define DB_BANK_HEIGHT(x)                        (((x) & 0x3) << 20)

#define DB_STENCIL_INFO					0x28044

#define DB_Z_READ_BASE					0x28048

#define DB_STENCIL_READ_BASE				0x2804c
@@ -951,6 +955,29 @@ 
#	define CB_SF_EXPORT_FULL			0

#	define CB_SF_EXPORT_NORM			1

#define	CB_COLOR0_ATTRIB				0x28c74

#       define CB_TILE_SPLIT(x)                         (((x) & 0x7) << 5)

#       define ADDR_SURF_TILE_SPLIT_64B                 0

#       define ADDR_SURF_TILE_SPLIT_128B                1

#       define ADDR_SURF_TILE_SPLIT_256B                2

#       define ADDR_SURF_TILE_SPLIT_512B                3

#       define ADDR_SURF_TILE_SPLIT_1KB                 4

#       define ADDR_SURF_TILE_SPLIT_2KB                 5

#       define ADDR_SURF_TILE_SPLIT_4KB                 6

#       define CB_NUM_BANKS(x)                          (((x) & 0x3) << 10)

#       define ADDR_SURF_2_BANK                         0

#       define ADDR_SURF_4_BANK                         1

#       define ADDR_SURF_8_BANK                         2

#       define ADDR_SURF_16_BANK                        3

#       define CB_BANK_WIDTH(x)                         (((x) & 0x3) << 13)

#       define ADDR_SURF_BANK_WIDTH_1                   0

#       define ADDR_SURF_BANK_WIDTH_2                   1

#       define ADDR_SURF_BANK_WIDTH_4                   2

#       define ADDR_SURF_BANK_WIDTH_8                   3

#       define CB_BANK_HEIGHT(x)                        (((x) & 0x3) << 16)

#       define ADDR_SURF_BANK_HEIGHT_1                  0

#       define ADDR_SURF_BANK_HEIGHT_2                  1

#       define ADDR_SURF_BANK_HEIGHT_4                  2

#       define ADDR_SURF_BANK_HEIGHT_8                  3

#define	CB_COLOR0_DIM					0x28c78

/* only CB0-7 blocks have these regs */

#define	CB_COLOR0_CMASK					0x28c7c
@@ -1137,7 +1164,11 @@ 
#	define SQ_SEL_1					5

#define SQ_TEX_RESOURCE_WORD5_0                         0x30014

#define SQ_TEX_RESOURCE_WORD6_0                         0x30018

#       define TEX_TILE_SPLIT(x)                        (((x) & 0x7) << 29)

#define SQ_TEX_RESOURCE_WORD7_0                         0x3001c

#       define TEX_BANK_WIDTH(x)                        (((x) & 0x3) << 8)

#       define TEX_BANK_HEIGHT(x)                       (((x) & 0x3) << 10)

#       define TEX_NUM_BANKS(x)                         (((x) & 0x3) << 16)



#define SQ_VTX_CONSTANT_WORD0_0				0x30000

#define SQ_VTX_CONSTANT_WORD1_0				0x30004