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Commit f36fc04e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk updates from Michael Turquette:
 "The clk framework changes for 4.3 are mostly updates to existing
  drivers and the addition of new clock drivers.  Stephen Boyd has also
  done a lot of subsystem-wide driver clean-ups (thanks!).  There are
  also fixes to the framework core and changes to better split clock
  provider drivers from clock consumer drivers"

* tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits)
  clk: s5pv210: add missing call to samsung_clk_of_add_provider()
  clk: pistachio: correct critical clock list
  clk: pistachio: Fix PLL rate calculation in integer mode
  clk: pistachio: Fix override of clk-pll settings from boot loader
  clk: pistachio: Fix 32bit integer overflows
  clk: tegra: Fix some static checker problems
  clk: qcom: Fix MSM8916 prng clock enable bit
  clk: Add missing header for 'bool' definition to clk-conf.h
  drivers/clk: appropriate __init annotation for const data
  clk: rockchip: register pll mux before pll itself
  clk: add bindings for the Ux500 clocks
  clk/ARM: move Ux500 PRCC bases to the device tree
  clk: remove duplicated code with __clk_set_parent_after
  clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)
  clk: Constify clk_hw argument to provider APIs
  clk: Hi6220: add stub clock driver
  dt-bindings: clk: Hi6220: Document stub clock driver
  dt-bindings: arm: Hi6220: add doc for SRAM controller
  clk: atlas7: fix pll missed divide NR in fraction mode
  clk: atlas7: fix bit field and its root clk for coresight_tpiu
  ...
parents 26f8b7ed ba300115

Documentation/clk.txt

+2 −6
Original line number Diff line number Diff line
@@ -71,12 +71,8 @@ the operations defined in clk.h: 
		long		(*round_rate)(struct clk_hw *hw,

						unsigned long rate,

						unsigned long *parent_rate);

		long		(*determine_rate)(struct clk_hw *hw,

						unsigned long rate,

						unsigned long min_rate,

						unsigned long max_rate,

						unsigned long *best_parent_rate,

						struct clk_hw **best_parent_clk);

		int		(*determine_rate)(struct clk_hw *hw,

						  struct clk_rate_request *req);

		int		(*set_parent)(struct clk_hw *hw, u8 index);

		u8		(*get_parent)(struct clk_hw *hw);

		int		(*set_rate)(struct clk_hw *hw,

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt

+18 −0
Original line number Diff line number Diff line
@@ -127,6 +127,24 @@ Example: 
		#clock-cells = <1>;

	};





Hisilicon Hi6220 SRAM controller



Required properties:

- compatible : "hisilicon,hi6220-sramctrl", "syscon"

- reg : Register address and size



Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several

SRAM banks for power management, modem, security, etc. Further, use "syscon"

managing the common sram which can be shared by multiple modules.



Example:

	/*for Hi6220*/

	sram: sram@fff80000 {

		compatible = "hisilicon,hi6220-sramctrl", "syscon";

		reg = <0x0 0xfff80000 0x0 0x12000>;

	};



-----------------------------------------------------------------------

Hisilicon HiP01 system controller

Documentation/devicetree/bindings/arm/sp810.txt

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SP810 System Controller

-----------------------



Required properties:



- compatible:	standard compatible string for a Primecell peripheral,

		see Documentation/devicetree/bindings/arm/primecell.txt

		for more details

		should be: "arm,sp810", "arm,primecell"



- reg:		standard registers property, physical address and size

		of the control registers



- clock-names:	from the common clock bindings, for more details see

		Documentation/devicetree/bindings/clock/clock-bindings.txt;

		should be: "refclk", "timclk", "apb_pclk"



- clocks:	from the common clock bindings, phandle and clock

		specifier pairs for the entries of clock-names property



- #clock-cells: from the common clock bindings;

		should be: <1>



- clock-output-names: from the common clock bindings;

		should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3"



- assigned-clocks: from the common clock binding;

		should be: clock specifier for each output clock of this

		provider node



- assigned-clock-parents: from the common clock binding;

		should be: phandle of input clock listed in clocks

		property with the highest frequency



Example:

	v2m_sysctl: sysctl@020000 {

		compatible = "arm,sp810", "arm,primecell";

		reg = <0x020000 0x1000>;

		clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;

		clock-names = "refclk", "timclk", "apb_pclk";

		#clock-cells = <1>;

		clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";

		assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;

		assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;



	};

Documentation/devicetree/bindings/clock/gpio-mux-clock.txt

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Binding for simple gpio clock multiplexer.



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be "gpio-mux-clock".

- clocks: list of two references to parent clocks.

- #clock-cells : from common clock binding; shall be set to 0.

- select-gpios : GPIO reference for selecting the parent clock.



Example:

	clock {

		compatible = "gpio-mux-clock";

		clocks = <&parentclk1>, <&parentclk2>;

		#clock-cells = <0>;

		select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;

	};

Documentation/devicetree/bindings/clock/hi6220-clock.txt

+18 −1
Original line number Diff line number Diff line
@@ -15,19 +15,36 @@ Required Properties: 
	- "hisilicon,hi6220-sysctrl"

	- "hisilicon,hi6220-mediactrl"

	- "hisilicon,hi6220-pmctrl"

	- "hisilicon,hi6220-stub-clk"



- reg: physical base address of the controller and length of memory mapped

  region.



- #clock-cells: should be 1.



For example:

Optional Properties:



- hisilicon,hi6220-clk-sram: phandle to the syscon managing the SoC internal sram;

  the driver need use the sram to pass parameters for frequency change.



- mboxes: use the label reference for the mailbox as the first parameter, the

  second parameter is the channel number.



Example 1:

	sys_ctrl: sys_ctrl@f7030000 {

		compatible = "hisilicon,hi6220-sysctrl", "syscon";

		reg = <0x0 0xf7030000 0x0 0x2000>;

		#clock-cells = <1>;

	};



Example 2:

	stub_clock: stub_clock {

		compatible = "hisilicon,hi6220-stub-clk";

		hisilicon,hi6220-clk-sram = <&sram>;

		#clock-cells = <1>;

		mboxes = <&mailbox 1>;

	};



Each clock is assigned an identifier and client nodes use this identifier

to specify the clock which they consume.